library ieee;
library unisim;

use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
-- Xilinx primitives (obufds)
use unisim.VComponents.all;

entity main is
    port (
        clk: in std_logic;

        dvi_d: out std_logic_vector(11 downto 0);
        dvi_clk_p: out std_logic;
        dvi_clk_n: out std_logic;
        dvi_hsync: out std_logic;
        dvi_vsync: out std_logic;
        dvi_de: out std_logic;
        dvi_reset: out std_logic;
        i2c_scl: inout std_logic;
        i2c_sda: inout std_logic;

        switch_center: in std_logic;
        rotary_up: in std_logic;
        rotary_down: in std_logic;
        rotary_push: in std_logic;

        led0: out std_logic;
        led1: out std_logic;
        led2: out std_logic;
        led4: out std_logic
    );
end main;

architecture Behavioral of main is
    signal clk_vga: std_logic;
    signal image_x: std_logic_vector(9 downto 0);
    signal image_y: std_logic_vector(9 downto 0);
    signal pixel_rgb: std_logic_vector(23 downto 0);
    signal dvi_clk: std_logic; -- connect vga_sync to dvi_clk_ds
    -- tmp
    signal hsync: std_logic;
    signal vsync: std_logic;
    signal de: std_logic;
begin
    -- convert the 100MHz to a 48MHz pixel clock
    clock_source: entity work.clock_source port map (
		CLKIN_IN => clk,
		CLKFX_OUT => clk_vga
	);

    dvi_clk_ds: obufds port map (
        O => dvi_clk_p,
        OB => dvi_clk_n,
        I => clk_vga
    );

    ch7301c: entity work.init_ch7301c generic map (
        input_clk => 48_000_000
    ) port map (
        clk => clk_vga,
        reset => switch_center,
        finished => open,
        error => open,
        i2c_scl => i2c_scl,
        i2c_sda => i2c_sda,
        dvi_reset => dvi_reset
    );

    vga_sync: entity work.vga port map (
        clk => clk_vga,
        x => image_x,
        y => image_y,
        pixel_rgb => pixel_rgb,
        dvi_d => dvi_d,
        dvi_clk => dvi_clk,
        dvi_hsync => hsync,
        dvi_vsync => vsync,
        dvi_de => de
    );

    image_generator_i: entity work.image_generator generic map (
        input_clk => 48_000_000
    ) port map (
        clk => clk_vga,
        x => image_x,
        y => image_y,
        ctrl_up => rotary_up,
        ctrl_down => rotary_down,
        rgb => pixel_rgb
    );

    dvi_hsync <= hsync;
    dvi_vsync <= vsync;
    dvi_de <= de;

    led0 <= switch_center;
    led1 <= dvi_clk;
    led2 <= hsync;
    led4 <= vsync;
end Behavioral;