library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; entity vga is port( clk: in std_logic; x, y: out std_logic_vector(9 downto 0); pixel_rgb: in std_logic_vector(23 downto 0); dvi_d: out std_logic_vector(11 downto 0); dvi_clk: out std_logic; dvi_hsync: out std_logic; dvi_vsync: out std_logic; dvi_de: out std_logic ); end vga; architecture behavioral of vga is signal second_batch: std_logic := '0'; signal hcount: std_logic_vector(9 downto 0) := (others => '0'); signal vcount: std_logic_vector(9 downto 0) := (others => '0'); signal data_enabled: std_logic; begin --dvi_clk <= clk; dvi_clk <= second_batch; dvi_de <= data_enabled; data_enabled <= '1' when hcount < 640 and vcount < 480 else '0'; dvi_hsync <= '0' when 656 <= hcount and hcount <= 720 else '1'; dvi_vsync <= '0' when 483 <= vcount and vcount <= 487 else '1'; x <= hcount when data_enabled = '1' and hcount < 640 else std_logic_vector(to_unsigned(639, 10)); y <= vcount when data_enabled = '1' and vcount < 480 else std_logic_vector(to_unsigned(479, 10)); data_output: process(clk) begin if rising_edge(clk) then if data_enabled = '1' then if second_batch = '0' then dvi_d <= pixel_rgb(11 downto 0); else dvi_d <= pixel_rgb(23 downto 12); end if; else dvi_d <= (others => '0'); end if; second_batch <= not second_batch; end if; end process data_output; hcounter: process(clk) begin if rising_edge(clk) and second_batch = '1' then if hcount < 799 then hcount <= hcount + 1; else hcount <= (others => '0'); end if; end if; end process hcounter; vcounter: process(clk, hcount) begin if rising_edge(clk) and second_batch = '1' and hcount = 700 then if vcount < 499 then vcount <= vcount + 1; else vcount <= (others => '0'); end if; end if; end process vcounter; end behavioral;