library ieee;

use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

entity ram_2port is
    generic (
        WIDTH_BITS: integer;
        DEPTH_BITS: integer
    );
    port (
        clk: in std_logic;
        we: in std_logic;
        wa: in std_logic_vector(DEPTH_BITS-1 downto 0);
        ra: in std_logic_vector(DEPTH_BITS-1 downto 0);
        di: in std_logic_vector(WIDTH_BITS-1 downto 0);
        do: out std_logic_vector(WIDTH_BITS-1 downto 0)
    );
end ram_2port;

architecture syn of ram_2port is
    type ram_type is array((2**DEPTH_BITS - 1) downto 0) of
                     std_logic_vector(WIDTH_BITS-1 downto 0);
    signal RAM: ram_type;
    signal read_a: std_logic_vector(ra'range);
begin

    process(clk)
    begin
        if rising_edge(clk) then
            if we = '1' then
                RAM(to_integer(unsigned(wa))) <= di;
            end if;

            read_a <= ra;
        end if;
    end process;

    do <= RAM(to_integer(unsigned(read_a)));

end syn;