From bee5a3a4718757648692540e164e375cb89eeed0 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Klemens=20Sch=C3=B6lhorn?= <klemens@schoelhorn.eu>
Date: Mon, 30 Apr 2018 03:45:35 +0200
Subject: [PATCH] Rename interface signals for easier integration

---
 main.vhd     |  8 ++++----
 terminal.vhd | 26 +++++++++++++-------------
 2 files changed, 17 insertions(+), 17 deletions(-)

diff --git a/main.vhd b/main.vhd
index c969374..b34e774 100644
--- a/main.vhd
+++ b/main.vhd
@@ -49,8 +49,8 @@ begin
 	);
 
     terminal: entity work.terminal port map (
-        clk => clk_vga,
-        reset => reset,
+        sys_clk => clk_vga,
+        sys_reset => reset,
         write_enable => write_enable,
         write_data => write_data,
         dvi_d => dvi_d,
@@ -60,8 +60,8 @@ begin
         dvi_vsync => dvi_vsync,
         dvi_de => dvi_de,
         dvi_reset => dvi_reset,
-        i2c_scl => i2c_scl,
-        i2c_sda => i2c_sda
+        dvi_i2c_scl => i2c_scl,
+        dvi_i2c_sda => i2c_sda
     );
 
     -- write an example text pattern to test the terminal
diff --git a/terminal.vhd b/terminal.vhd
index 462052d..745dcf8 100644
--- a/terminal.vhd
+++ b/terminal.vhd
@@ -12,8 +12,8 @@ entity terminal is
         clk_f: integer := 48_000_000
     );
     port (
-        clk: in std_logic;
-        reset: in std_logic;
+        sys_clk: in std_logic;
+        sys_reset: in std_logic;
 
         write_enable: in std_logic;
         write_data: in std_logic_vector(7 downto 0);
@@ -25,8 +25,8 @@ entity terminal is
         dvi_vsync: out std_logic;
         dvi_de: out std_logic;
         dvi_reset: out std_logic;
-        i2c_scl: inout std_logic;
-        i2c_sda: inout std_logic
+        dvi_i2c_scl: inout std_logic;
+        dvi_i2c_sda: inout std_logic
     );
 end terminal;
 
@@ -50,10 +50,10 @@ begin
 
     -- writes the next character, advances the cursor and saves the length of
     -- the current row before jumping to the next one
-    process(clk)
+    process(sys_clk)
         variable next_line: unsigned(5 downto 0);
     begin
-        if rising_edge(clk) then
+        if rising_edge(sys_clk) then
             -- we write to the current cursor position and simply pass the data
             -- through (but CR and LF are ignored, so charbuf_we is 0 by default)
             charbuf_we <= '0';
@@ -102,7 +102,7 @@ begin
     end process;
 
     dvi_clk_ds: obufds port map (
-        I => clk,
+        I => sys_clk,
         O => dvi_clk_p,
         OB => dvi_clk_n
     );
@@ -110,17 +110,17 @@ begin
     init_ch7301c: entity work.init_ch7301c generic map (
         input_clk => clk_f
     ) port map (
-        clk => clk,
-        reset => reset,
+        clk => sys_clk,
+        reset => sys_reset,
         finished => open,
         error => open,
-        i2c_scl => i2c_scl,
-        i2c_sda => i2c_sda,
+        i2c_scl => dvi_i2c_scl,
+        i2c_sda => dvi_i2c_sda,
         dvi_reset => dvi_reset
     );
 
     vga: entity work.vga port map (
-        clk => clk,
+        clk => sys_clk,
         x => image_x,
         y => image_y,
         pixel_rgb => pixel_rgb,
@@ -133,7 +133,7 @@ begin
     framebuffer: entity work.framebuffer generic map (
         input_clk => clk_f
     ) port map (
-        clk => clk,
+        clk => sys_clk,
         x => image_x,
         y => image_y,
         rgb => pixel_rgb,