riscv/terminal
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Implement single character write interface

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This basic interface just moves the cursor to the next position after
writing a character and supports CR and LF as special chars for now.
This commit is contained in:
Klemens Schölhorn
2018-04-24 23:44:13 +02:00
parent 0aad663c33
commit 8ee7a1c463
3 changed files with 69 additions and 42 deletions
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52
framebuffer.vhd
View File

@@ -16,7 +16,11 @@ entity framebuffer is
x: in std_logic_vector(9 downto 0);
y: in std_logic_vector(8 downto 0);
rgb: out std_logic_vector(23 downto 0)
rgb: out std_logic_vector(23 downto 0);
write_enable: std_logic;
write_address: std_logic_vector(12 downto 0);
write_data: std_logic_vector(7 downto 0)
);
end framebuffer;
@@ -41,6 +45,7 @@ architecture logic of framebuffer is
constant font: rom_type := read_font("font.hex");
signal read_address: std_logic_vector(12 downto 0);
signal current_char: std_logic_vector(7 downto 0);
signal current_glyph: std_logic_vector(63 downto 0);
@@ -49,52 +54,17 @@ architecture logic of framebuffer is
constant glyph_pos_length: integer := 2;
type glyph_pos_type is array(1 to glyph_pos_length) of integer range 0 to 63;
signal glyph_pos: glyph_pos_type;
signal write_x: unsigned(6 downto 0);
signal write_y: unsigned(5 downto 0);
signal write_value: std_logic_vector(7 downto 0);
signal ra: std_logic_vector(12 downto 0);
signal wa: std_logic_vector(12 downto 0);
begin
ra <= x(9 downto 3) & y(8 downto 3);
wa <= std_logic_vector(write_x) & std_logic_vector(write_y);
write_value <= "0" & std_logic_vector(write_x + 32);
cycle_write_location:
process(clk)
constant max_delay: integer := 2000000;
variable delay: integer range 0 to max_delay;
begin
if rising_edge(clk) then
if delay = max_delay then
delay := 0;
if write_x = 79 then
write_x <= (others => '0');
if write_y = 59 then
write_y <= (others => '0');
else
write_y <= write_y + 1;
end if;
else
write_x <= write_x + 1;
end if;
else
delay := delay + 1;
end if;
end if;
end process cycle_write_location;
read_address <= x(9 downto 3) & y(8 downto 3);
terminal_buffer: entity work.terminal_buffer port map (
clk => clk,
ra => ra,
ra => read_address,
do => current_char,
we => '1',
wa => wa,
di => write_value
we => write_enable,
wa => write_address,
di => write_data
);
process(clk)

3
main.vhd
View File

@@ -51,6 +51,9 @@ begin
clk => clk_vga,
reset => reset,
write_enable => '0',
write_data => x"00",
dvi_d => dvi_d,
dvi_clk_p => dvi_clk_p,
dvi_clk_n => dvi_clk_n,

56
terminal.vhd
View File

@@ -15,6 +15,9 @@ entity terminal is
clk: in std_logic;
reset: in std_logic;
write_enable: in std_logic;
write_data: in std_logic_vector(7 downto 0);
dvi_d: out std_logic_vector(11 downto 0);
dvi_clk_p: out std_logic;
dvi_clk_n: out std_logic;
@@ -31,8 +34,56 @@ architecture syn of terminal is
signal image_x: std_logic_vector(9 downto 0);
signal image_y: std_logic_vector(8 downto 0);
signal pixel_rgb: std_logic_vector(23 downto 0);
signal fb_write_enable: std_logic;
signal fb_write_address: std_logic_vector(12 downto 0);
signal fb_write_data: std_logic_vector(7 downto 0);
signal write_x: unsigned(6 downto 0);
signal write_y: unsigned(5 downto 0);
begin
fb_write_address <= std_logic_vector(write_x) & std_logic_vector(write_y);
process(clk)
variable next_line: unsigned(5 downto 0);
begin
if rising_edge(clk) then
fb_write_enable <= '0';
fb_write_data <= write_data;
-- calculate next line
if write_y = 59 then
next_line := (others => '0');
else
next_line := write_y + 1;
end if;
if write_enable = '1' then
fb_write_enable <= '1';
if write_x = 79 then
write_x <= (others => '0');
write_y <= next_line;
else
write_x <= write_x + 1;
end if;
-- carriage return
if write_data = x"0d" then
fb_write_enable <= '0';
write_x <= (others => '0');
end if;
-- line feed (implicit CR)
if write_data = x"0a" then
fb_write_enable <= '0';
write_x <= (others => '0');
write_y <= next_line;
end if;
end if;
end if;
end process;
dvi_clk_ds: obufds port map (
I => clk,
O => dvi_clk_p,
@@ -68,7 +119,10 @@ begin
clk => clk,
x => image_x,
y => image_y,
rgb => pixel_rgb
rgb => pixel_rgb,
write_enable => fb_write_enable,
write_address => fb_write_address,
write_data => fb_write_data
);
end syn;