Add minimal keyboard controller that counts received bytes

dvi_test.xise

@@ -17,7 +17,7 @@
   <files>
     <file xil_pn:name="vga.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
     </file>
     <file xil_pn:name="vga_test.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
@@ -27,26 +27,34 @@
     </file>
     <file xil_pn:name="i2c_master.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="64"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
     </file>
     <file xil_pn:name="main.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="65"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
     </file>
     <file xil_pn:name="ipcore_dir/clock_source.xaw" xil_pn:type="FILE_XAW">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="106"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
     </file>
     <file xil_pn:name="init_ch7301c.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="112"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
     </file>
     <file xil_pn:name="main.ucf" xil_pn:type="FILE_UCF">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
     <file xil_pn:name="image_generator.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
+    </file>
+    <file xil_pn:name="keyboard.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="153"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
+    </file>
+    <file xil_pn:name="ps2.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
     </file>
   </files>
 

keyboard.vhd

@@ -0,0 +1,85 @@
+library ieee;
+library unisim;
+
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+entity keyboard is
+    generic (
+        input_clk: integer
+    );
+    port (
+        clk: in std_logic;
+        reset: in std_logic;
+
+        bytes_received: out std_logic_vector(5 downto 0);
+
+        ps2_scl: inout std_logic;
+        ps2_sda: inout std_logic
+    );
+end keyboard;
+
+architecture Behavioral of keyboard is
+    signal ps2_reset_n: std_logic;
+    signal ps2_clear_data_available: std_logic;
+    signal ps2_data_available: std_logic;
+    signal ps2_data_available_old: std_logic;
+
+    signal byte_count: std_logic_vector(5 downto 0);
+begin
+
+    ps2_host: entity work.ps2 port map (
+        clk_i => clk,
+        rst_i => ps2_reset_n,
+
+        data_o => open,
+        data_i => "00000000",
+        ibf_clr_i => ps2_clear_data_available,
+        obf_set_i => '0', -- we don't want to write anything
+        ibf_o => ps2_data_available,
+        obf_o => open,
+
+        frame_err_o => open, -- ignore errors for now
+        parity_err_o => open,
+        busy_o => open,
+        err_clr_i => '0',
+
+        wdt_o => open,
+
+        ps2_clk_io => ps2_scl,
+        ps2_data_io => ps2_sda
+    );
+
+    -- count bytes received
+    main: process(clk, reset)
+        constant max_delay: integer := input_clk / 200_000; -- 5µs
+        variable delay: integer range 0 to max_delay := 0;
+    begin
+        if reset = '1' then
+            delay := 0;
+            byte_count <= "000000";
+            -- reset component
+            ps2_reset_n <= '0';
+        elsif rising_edge(clk) then
+            if delay = 5 then
+                -- init component
+                ps2_reset_n <= '1';
+                delay := delay + 1;
+            elsif delay = max_delay then
+                ps2_clear_data_available <= '0';
+                ps2_data_available_old <= ps2_data_available;
+                if ps2_data_available_old = '0' and ps2_data_available = '1' then
+                    -- count rising edges on ps2_data_available:
+                    byte_count <= byte_count + 1;
+                    ps2_clear_data_available <= '1';
+                end if;
+            else
+                delay := delay + 1;
+            end if;
+        end if;
+    end process main;
+
+    bytes_received <= byte_count;
+
+end Behavioral;

main.ucf

@@ -20,6 +20,10 @@ NET "dvi_reset" LOC = AK6;
 NET "i2c_scl" LOC = U27;
 NET "i2c_sda" LOC = T29;
 
+# PS/2 Interface
+NET "ps2_scl" LOC = T26;
+NET "ps2_sda" LOC = T25;
+
 NET "clk" LOC = AH15;
 NET "clk" PERIOD = 100 MHz HIGH 50%;
 
@@ -28,7 +32,11 @@ NET "rotary_up" LOC = AH30;
 NET "rotary_down" LOC = AG30;
 NET "rotary_push" LOC = AH29;
 
-NET "led0" LOC = H18;
+NET "led(0)" LOC = H18; # no DCI
-NET "led1" LOC = L18;
+NET "led(1)" LOC = L18; # no DCI
-NET "led2" LOC = G15;
+NET "led(2)" LOC = G15; # no DCI
-NET "led4" LOC = G16;
+NET "led(3)" LOC = AD26;
+NET "led(4)" LOC = G16; # no DCI
+NET "led(5)" LOC = AD25;
+NET "led(6)" LOC = AD24;
+NET "led(7)" LOC = AE24;

main.vhd

@@ -21,11 +21,16 @@ entity main is
         i2c_scl: inout std_logic;
         i2c_sda: inout std_logic;
 
+        ps2_scl: inout std_logic;
+        ps2_sda: inout std_logic;
+
         switch_center: in std_logic;
         rotary_up: in std_logic;
         rotary_down: in std_logic;
         rotary_push: in std_logic;
 
+        led: out std_logic_vector(7 downto 0);
+
         led0: out std_logic;
         led1: out std_logic;
         led2: out std_logic;
@@ -91,12 +96,23 @@ begin
         rgb => pixel_rgb
     );
 
+    keyboard_i: entity work.keyboard generic map (
+        input_clk => 48_000_000
+    ) port map (
+        clk => clk_vga,
+        reset => switch_center,
+        bytes_received => led(5 downto 0),
+        ps2_scl => ps2_scl,
+        ps2_sda => ps2_sda
+    );
+
     dvi_hsync <= hsync;
     dvi_vsync <= vsync;
     dvi_de <= de;
 
-    led0 <= switch_center;
+    led(7) <= switch_center;
-    led1 <= dvi_clk;
+    led(6) <= '0';
-    led2 <= hsync;
+    --led1 <= dvi_clk;
-    led4 <= vsync;
+    --led2 <= hsync;
+    --led4 <= vsync;
 end Behavioral;