86 lines
2.3 KiB
VHDL
86 lines
2.3 KiB
VHDL
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library ieee;
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library unisim;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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entity keyboard is
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generic (
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input_clk: integer
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);
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port (
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clk: in std_logic;
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reset: in std_logic;
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bytes_received: out std_logic_vector(5 downto 0);
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ps2_scl: inout std_logic;
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ps2_sda: inout std_logic
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);
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end keyboard;
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architecture Behavioral of keyboard is
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signal ps2_reset_n: std_logic;
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signal ps2_clear_data_available: std_logic;
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signal ps2_data_available: std_logic;
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signal ps2_data_available_old: std_logic;
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signal byte_count: std_logic_vector(5 downto 0);
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begin
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ps2_host: entity work.ps2 port map (
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clk_i => clk,
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rst_i => ps2_reset_n,
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data_o => open,
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data_i => "00000000",
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ibf_clr_i => ps2_clear_data_available,
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obf_set_i => '0', -- we don't want to write anything
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ibf_o => ps2_data_available,
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obf_o => open,
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frame_err_o => open, -- ignore errors for now
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parity_err_o => open,
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busy_o => open,
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err_clr_i => '0',
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wdt_o => open,
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ps2_clk_io => ps2_scl,
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ps2_data_io => ps2_sda
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);
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-- count bytes received
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main: process(clk, reset)
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constant max_delay: integer := input_clk / 200_000; -- 5µs
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variable delay: integer range 0 to max_delay := 0;
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begin
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if reset = '1' then
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delay := 0;
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byte_count <= "000000";
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-- reset component
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ps2_reset_n <= '0';
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elsif rising_edge(clk) then
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if delay = 5 then
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-- init component
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ps2_reset_n <= '1';
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delay := delay + 1;
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elsif delay = max_delay then
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ps2_clear_data_available <= '0';
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ps2_data_available_old <= ps2_data_available;
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if ps2_data_available_old = '0' and ps2_data_available = '1' then
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-- count rising edges on ps2_data_available:
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byte_count <= byte_count + 1;
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ps2_clear_data_available <= '1';
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end if;
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else
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delay := delay + 1;
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end if;
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end if;
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end process main;
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bytes_received <= byte_count;
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end Behavioral;
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