38 lines
884 B
VHDL
38 lines
884 B
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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entity terminal_buffer is
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port (
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clk: in std_logic;
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we: in std_logic;
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wa: in std_logic_vector(12 downto 0);
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ra: in std_logic_vector(12 downto 0);
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di: in std_logic_vector(7 downto 0);
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do: out std_logic_vector(7 downto 0)
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);
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end terminal_buffer;
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architecture syn of terminal_buffer is
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type ram_type is array((2**13 - 1) downto 0) of std_logic_vector(7 downto 0);
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signal RAM: ram_type;
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signal read_a: std_logic_vector(ra'range);
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begin
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process(clk)
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begin
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if rising_edge(clk) then
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if we = '1' then
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RAM(to_integer(unsigned(wa))) <= di;
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end if;
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read_a <= ra;
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end if;
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end process;
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do <= RAM(to_integer(unsigned(read_a)));
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end syn;
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