76 lines
1.7 KiB
VHDL
76 lines
1.7 KiB
VHDL
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library ieee;
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library unisim;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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-- Xilinx primitives (obufds)
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use unisim.VComponents.all;
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entity terminal is
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generic (
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clk_f: integer
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);
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port (
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clk: in std_logic;
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reset: in std_logic;
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dvi_d: out std_logic_vector(11 downto 0);
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dvi_clk_p: out std_logic;
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dvi_clk_n: out std_logic;
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dvi_hsync: out std_logic;
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dvi_vsync: out std_logic;
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dvi_de: out std_logic;
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dvi_reset: out std_logic;
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i2c_scl: inout std_logic;
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i2c_sda: inout std_logic
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);
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end terminal;
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architecture syn of terminal is
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signal image_x: std_logic_vector(9 downto 0);
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signal image_y: std_logic_vector(8 downto 0);
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signal pixel_rgb: std_logic_vector(23 downto 0);
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begin
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dvi_clk_ds: obufds port map (
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I => clk,
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O => dvi_clk_p,
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OB => dvi_clk_n
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);
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init_ch7301c: entity work.init_ch7301c generic map (
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input_clk => clk_f
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) port map (
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clk => clk,
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reset => reset,
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finished => open,
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error => open,
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i2c_scl => i2c_scl,
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i2c_sda => i2c_sda,
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dvi_reset => dvi_reset
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);
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vga: entity work.vga port map (
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clk => clk,
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x => image_x,
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y => image_y,
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pixel_rgb => pixel_rgb,
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dvi_d => dvi_d,
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dvi_hsync => dvi_hsync,
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dvi_vsync => dvi_vsync,
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dvi_de => dvi_de
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);
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framebuffer: entity work.framebuffer generic map (
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input_clk => clk_f
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) port map (
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clk => clk,
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x => image_x,
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y => image_y,
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rgb => pixel_rgb
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);
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end syn;
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