This website requires JavaScript.
Explore
Help
Sign In
riscv
/
sifive-blocks
Watch
1
Star
0
Fork
0
You've already forked sifive-blocks
Code
Releases
Activity
b3f656affe
sifive-blocks
/
src
/
main
/
scala
/
devices
History
Megan Wachs
b3f656affe
UART: actually return the pins, not just the module. We should do this for the other peripherals as well
2017-06-12 18:08:35 -07:00
..
gpio
periphery: convert periphery bundle traits to work with system-level multi-io module
2017-06-12 16:57:47 -07:00
i2c
GPIO/SPI/I2C: Add sync stages in place of dummy variable since we need them and they are more useful.
2017-06-12 17:53:51 -07:00
mockaon
periphery: convert periphery bundle traits to work with system-level multi-io module
2017-06-12 16:57:47 -07:00
pwm
periphery: convert periphery bundle traits to work with system-level multi-io module
2017-06-12 16:57:47 -07:00
spi
GPIO/SPI/I2C: Add sync stages in place of dummy variable since we need them and they are more useful.
2017-06-12 17:53:51 -07:00
uart
UART: actually return the pins, not just the module. We should do this for the other peripherals as well
2017-06-12 18:08:35 -07:00
xilinxvc707mig
periphery: convert periphery bundle traits to work with system-level multi-io module
2017-06-12 16:57:47 -07:00
xilinxvc707pciex1
periphery: convert periphery bundle traits to work with system-level multi-io module
2017-06-12 16:57:47 -07:00