52 lines
1.6 KiB
Scala
52 lines
1.6 KiB
Scala
// See LICENSE for license details.
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package sifive.blocks.util
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import Chisel._
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object ShiftRegisterInit {
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def apply[T <: Data](in: T, n: Int, init: T): T =
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(0 until n).foldLeft(in) {
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case (next, _) => Reg(next, next = next, init = init)
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}
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}
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object ShiftRegister
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{
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/** Returns the n-cycle delayed version of the input signal.
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*
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* @param in input to delay
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* @param n number of cycles to delay
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* @param en enable the shift
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* @param name set the elaborated name of the registers.
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*/
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def apply[T <: Chisel.Data](in: T, n: Int, en: Chisel.Bool = Chisel.Bool(true), name: Option[String] = None): T = {
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// The order of tests reflects the expected use cases.
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if (n != 0) {
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val r = Chisel.RegEnable(apply(in, n-1, en, name), en)
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if (name.isDefined) r.suggestName(s"${name.get}_sync_${n-1}")
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r
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} else {
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in
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}
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}
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/** Returns the n-cycle delayed version of the input signal with reset initialization.
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*
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* @param in input to delay
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* @param n number of cycles to delay
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* @param resetData reset value for each register in the shift
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* @param en enable the shift
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* @param name set the elaborated name of the registers.
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*/
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def apply[T <: Chisel.Data](in: T, n: Int, resetData: T, en: Chisel.Bool, name: Option[String]): T = {
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// The order of tests reflects the expected use cases.
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if (n != 0) {
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val r = Chisel.RegEnable(apply(in, n-1, resetData, en, name), resetData, en)
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if (name.isDefined) r.suggestName(s"${name.get}_sync_${n-1}")
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r
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} else {
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in
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}
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}
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}
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