23 lines
327 B
Verilog
23 lines
327 B
Verilog
// See LICENSE for license details.
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module SRLatch (
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input set,
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input reset,
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output q
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);
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reg latch;
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// synopsys async_set_reset "set"
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// synopsys one_hot "set, reset"
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always @(set or reset)
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begin
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if (set)
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latch <= 1'b1;
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else if (reset)
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latch <= 1'b0;
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end
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assign q = latch;
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endmodule
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