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sifive-blocks/vsrc/SRLatch.v
2016-11-29 04:08:44 -08:00

23 lines
327 B
Verilog

// See LICENSE for license details.
module SRLatch (
input set,
input reset,
output q
);
reg latch;
// synopsys async_set_reset "set"
// synopsys one_hot "set, reset"
always @(set or reset)
begin
if (set)
latch <= 1'b1;
else if (reset)
latch <= 1'b0;
end
assign q = latch;
endmodule