34 lines
1014 B
Scala
34 lines
1014 B
Scala
// See LICENSE for license details.
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package sifive.blocks.devices.i2c
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import Chisel._
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import config.Field
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import diplomacy.LazyModule
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import rocketchip.{HasTopLevelNetworks,HasTopLevelNetworksBundle,HasTopLevelNetworksModule}
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import uncore.tilelink2.TLFragmenter
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case object PeripheryI2CKey extends Field[Seq[I2CParams]]
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trait HasPeripheryI2C extends HasTopLevelNetworks {
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val i2cParams = p(PeripheryI2CKey)
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val i2c = i2cParams map { params =>
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val i2c = LazyModule(new TLI2C(peripheryBusBytes, params))
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i2c.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
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intBus.intnode := i2c.intnode
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i2c
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}
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}
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trait HasPeripheryI2CBundle extends HasTopLevelNetworksBundle{
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val outer: HasPeripheryI2C
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val i2cs = Vec(outer.i2cParams.size, new I2CPort)
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}
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trait HasPeripheryI2CModule extends HasTopLevelNetworksModule {
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val outer: HasPeripheryI2C
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val io: HasPeripheryI2CBundle
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(io.i2cs zip outer.i2c).foreach { case (io, device) =>
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io <> device.module.io.port
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}
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}
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