55 lines
1.3 KiB
Scala
55 lines
1.3 KiB
Scala
// See LICENSE for license details.
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package sifive.blocks.devices.uart
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import Chisel._
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import config._
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import diplomacy._
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import uncore.tilelink2._
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import rocketchip._
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import sifive.blocks.devices.gpio.{GPIOPin, GPIOOutputPinCtrl, GPIOInputPinCtrl}
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import sifive.blocks.util.ShiftRegisterInit
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trait PeripheryUART {
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this: TopNetwork {
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val uartConfigs: Seq[UARTConfig]
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} =>
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val uart = uartConfigs.zipWithIndex.map { case (c, i) =>
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val uart = LazyModule(new UART(c))
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uart.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
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intBus.intnode := uart.intnode
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uart
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}
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}
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trait PeripheryUARTBundle {
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this: { val uartConfigs: Seq[UARTConfig] } =>
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val uarts = Vec(uartConfigs.size, new UARTPortIO)
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}
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trait PeripheryUARTModule {
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this: TopNetworkModule {
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val outer: PeripheryUART
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val io: PeripheryUARTBundle
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} =>
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(io.uarts zip outer.uart).foreach { case (io, device) =>
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io <> device.module.io.port
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}
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}
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class UARTPinsIO extends Bundle {
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val rxd = new GPIOPin
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val txd = new GPIOPin
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}
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class UARTGPIOPort(syncStages: Int = 0) extends Module {
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val io = new Bundle{
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val uart = new UARTPortIO().flip()
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val pins = new UARTPinsIO
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}
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GPIOOutputPinCtrl(io.pins.txd, io.uart.txd)
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val rxd = GPIOInputPinCtrl(io.pins.rxd)
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io.uart.rxd := ShiftRegisterInit(rxd, syncStages, Bool(true))
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}
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