48 lines
1.2 KiB
Scala
48 lines
1.2 KiB
Scala
// See LICENSE for license details.
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package sifive.blocks.util
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import Chisel._
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import freechips.rocketchip.regmapper._
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// MSB indicates full status
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object NonBlockingEnqueue {
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def apply(enq: DecoupledIO[UInt], regWidth: Int = 32): Seq[RegField] = {
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val enqWidth = enq.bits.getWidth
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val quash = Wire(Bool())
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require(enqWidth > 0)
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require(regWidth > enqWidth)
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Seq(
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RegField(enqWidth,
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RegReadFn(UInt(0)),
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RegWriteFn((valid, data) => {
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enq.valid := valid && !quash
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enq.bits := data
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Bool(true)
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})),
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RegField(regWidth - enqWidth - 1),
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RegField(1,
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!enq.ready,
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RegWriteFn((valid, data) => {
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quash := valid && data(0)
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Bool(true)
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})))
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}
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}
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// MSB indicates empty status
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object NonBlockingDequeue {
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def apply(deq: DecoupledIO[UInt], regWidth: Int = 32): Seq[RegField] = {
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val deqWidth = deq.bits.getWidth
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require(deqWidth > 0)
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require(regWidth > deqWidth)
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Seq(
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RegField.r(deqWidth,
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RegReadFn(ready => {
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deq.ready := ready
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(Bool(true), deq.bits)
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})),
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RegField(regWidth - deqWidth - 1),
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RegField.r(1, !deq.valid))
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}
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}
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