riscv/sifive-blocks
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Refactor package hierarchy. (#25)

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This commit is contained in:
Henry Cook
2017-07-07 10:48:57 -07:00
committed by GitHub
parent 66b2fd11bd
commit fb9dd31374
27 changed files with 100 additions and 99 deletions
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12
src/main/scala/devices/uart/UART.scala
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@ -2,10 +2,12 @@
package sifive.blocks.devices.uart
import Chisel._
import config._
import regmapper._
import uncore.tilelink2._
import util._
import freechips.rocketchip.chip.RTCPeriod
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy.DTSTimebase
import freechips.rocketchip.regmapper._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
import sifive.blocks.util.{NonBlockingEnqueue, NonBlockingDequeue}
@ -203,7 +205,7 @@ trait HasUARTTopModuleContents extends Module with HasUARTParameters with HasReg
val rxm = Module(new UARTRx(params))
val rxq = Module(new Queue(rxm.io.out.bits, uartNRxEntries))
val divinit = p(diplomacy.DTSTimebase) * p(rocketchip.RTCPeriod) / 115200
val divinit = p(DTSTimebase) * p(RTCPeriod) / 115200
val div = Reg(init = UInt(divinit, uartDivisorBits))
private val stopCountBits = log2Up(uartStopBits)

9
src/main/scala/devices/uart/UARTPeriphery.scala
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@ -2,11 +2,10 @@
package sifive.blocks.devices.uart
import Chisel._
import config.Field
import diplomacy.{LazyModule, LazyMultiIOModuleImp}
import rocketchip.HasSystemNetworks
import uncore.tilelink2.TLFragmenter
import freechips.rocketchip.config.Field
import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
import freechips.rocketchip.chip.HasSystemNetworks
import freechips.rocketchip.tilelink.TLFragmenter
import sifive.blocks.devices.gpio.{GPIOPin, GPIOOutputPinCtrl, GPIOInputPinCtrl}
import sifive.blocks.util.ShiftRegisterInit