riscv/sifive-blocks
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Refactor package hierarchy. (#25)

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This commit is contained in:
Henry Cook
2017-07-07 10:48:57 -07:00
committed by GitHub
parent 66b2fd11bd
commit fb9dd31374
27 changed files with 100 additions and 99 deletions
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2
src/main/scala/devices/spi/SPIBundle.scala
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@ -2,7 +2,7 @@
package sifive.blocks.devices.spi
import Chisel._
import util.GenericParameterizedBundle
import freechips.rocketchip.util.GenericParameterizedBundle
abstract class SPIBundle(val c: SPIParamsBase) extends GenericParameterizedBundle(c) {
override def cloneType: SPIBundle.this.type =

10
src/main/scala/devices/spi/SPIPeriphery.scala
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@ -2,11 +2,11 @@
package sifive.blocks.devices.spi
import Chisel._
import config.Field
import diplomacy.{LazyModule,LazyMultiIOModuleImp}
import rocketchip.HasSystemNetworks
import uncore.tilelink2.{TLFragmenter,TLWidthWidget}
import util.HeterogeneousBag
import freechips.rocketchip.config.Field
import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp}
import freechips.rocketchip.chip.HasSystemNetworks
import freechips.rocketchip.tilelink.{TLFragmenter,TLWidthWidget}
import freechips.rocketchip.util.HeterogeneousBag
case object PeripherySPIKey extends Field[Seq[SPIParams]]

12
src/main/scala/devices/spi/TLSPI.scala
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@ -2,11 +2,11 @@
package sifive.blocks.devices.spi
import Chisel._
import config._
import diplomacy._
import regmapper._
import uncore.tilelink2._
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.regmapper._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util.HeterogeneousBag
import sifive.blocks.util.{NonBlockingEnqueue, NonBlockingDequeue}
trait SPIParamsBase {
@ -47,7 +47,7 @@ case class SPIParams(
require(sampleDelay >= 0)
}
class SPITopBundle(val i: util.HeterogeneousBag[Vec[Bool]], val r: util.HeterogeneousBag[TLBundle]) extends Bundle
class SPITopBundle(val i: HeterogeneousBag[Vec[Bool]], val r: HeterogeneousBag[TLBundle]) extends Bundle
class SPITopModule[B <: SPITopBundle](c: SPIParamsBase, bundle: => B, outer: TLSPIBase)
extends LazyModuleImp(outer) {

11
src/main/scala/devices/spi/TLSPIFlash.scala
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@ -2,10 +2,11 @@
package sifive.blocks.devices.spi
import Chisel._
import config._
import diplomacy._
import regmapper._
import uncore.tilelink2._
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.regmapper._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util.HeterogeneousBag
trait SPIFlashParamsBase extends SPIParamsBase {
val fAddress: BigInt
@ -38,7 +39,7 @@ case class SPIFlashParams(
require(sampleDelay >= 0)
}
class SPIFlashTopBundle(i: util.HeterogeneousBag[Vec[Bool]], r: util.HeterogeneousBag[TLBundle], val f: util.HeterogeneousBag[TLBundle]) extends SPITopBundle(i, r)
class SPIFlashTopBundle(i: HeterogeneousBag[Vec[Bool]], r: HeterogeneousBag[TLBundle], val f: HeterogeneousBag[TLBundle]) extends SPITopBundle(i, r)
class SPIFlashTopModule[B <: SPIFlashTopBundle]
(c: SPIFlashParamsBase, bundle: => B, outer: TLSPIFlashBase)