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Refactor package hierarchy. (#25)

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This commit is contained in:
Henry Cook
2017-07-07 10:48:57 -07:00
committed by GitHub
parent 66b2fd11bd
commit fb9dd31374
27 changed files with 100 additions and 99 deletions
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6
src/main/scala/devices/mockaon/MockAON.scala
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@ -2,9 +2,9 @@
package sifive.blocks.devices.mockaon
import Chisel._
import config._
import regmapper._
import uncore.tilelink2._
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.regmapper._
import freechips.rocketchip.tilelink._
import sifive.blocks.util.GenericTimer

10
src/main/scala/devices/mockaon/MockAONPeriphery.scala
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@ -2,11 +2,11 @@
package sifive.blocks.devices.mockaon
import Chisel._
import config.Field
import diplomacy.{LazyModule, LazyMultiIOModuleImp}
import rocketchip.{HasSystemNetworks, HasCoreplexRISCVPlatform}
import uncore.tilelink2.{IntXing, TLAsyncCrossingSource, TLFragmenter}
import util.ResetCatchAndSync
import freechips.rocketchip.config.Field
import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
import freechips.rocketchip.chip.{HasSystemNetworks, HasCoreplexRISCVPlatform}
import freechips.rocketchip.tilelink.{IntXing, TLAsyncCrossingSource, TLFragmenter}
import freechips.rocketchip.util.ResetCatchAndSync
case object PeripheryMockAONKey extends Field[MockAONParams]

9
src/main/scala/devices/mockaon/MockAONWrapper.scala
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@ -2,12 +2,13 @@
package sifive.blocks.devices.mockaon
import Chisel._
import config._
import diplomacy._
import uncore.tilelink2._
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
import sifive.blocks.devices.gpio.{GPIOPin, GPIOOutputPinCtrl, GPIOInputPinCtrl}
import sifive.blocks.util.{DeglitchShiftRegister, ResetCatchAndSync}
import util._
/* The wrapper handles the Clock and Reset Generation for The AON block itself,
and instantiates real pad controls (aka pull-ups)*/

2
src/main/scala/devices/mockaon/PMU.scala
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@ -3,7 +3,7 @@ package sifive.blocks.devices.mockaon
import Chisel._
import Chisel.ImplicitConversions._
import util._
import freechips.rocketchip.util._
import sifive.blocks.util.SRLatch
import sifive.blocks.util.{SlaveRegIF}

2
src/main/scala/devices/mockaon/WatchdogTimer.scala
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@ -3,7 +3,7 @@ package sifive.blocks.devices.mockaon
import Chisel._
import Chisel.ImplicitConversions._
import util.AsyncResetReg
import freechips.rocketchip.util.AsyncResetReg
import sifive.blocks.util.{SlaveRegIF, GenericTimer}