riscv/sifive-blocks
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Refactor package hierarchy. (#25)

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This commit is contained in:
Henry Cook
2017-07-07 10:48:57 -07:00
committed by GitHub
parent 66b2fd11bd
commit fb9dd31374
27 changed files with 100 additions and 99 deletions
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8
src/main/scala/devices/gpio/GPIO.scala
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@ -2,10 +2,10 @@
package sifive.blocks.devices.gpio
import Chisel._
import config.Parameters
import regmapper._
import uncore.tilelink2._
import util.{AsyncResetRegVec, GenericParameterizedBundle}
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.regmapper._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util.{AsyncResetRegVec, GenericParameterizedBundle}
case class GPIOParams(address: BigInt, width: Int, includeIOF: Boolean = false)