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RegMapFIFO: amoor.w can do thread-safe TX

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This commit is contained in:
Wesley W. Terpstra 2016-12-02 17:48:17 -08:00
parent b8ecb7853b
commit ca7555bd4d
1 changed files with 8 additions and 2 deletions
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10
src/main/scala/util/RegMapFIFO.scala
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@ -8,18 +8,24 @@ import regmapper._
object NonBlockingEnqueue { object NonBlockingEnqueue {
def apply(enq: DecoupledIO[UInt], regWidth: Int = 32): Seq[RegField] = { def apply(enq: DecoupledIO[UInt], regWidth: Int = 32): Seq[RegField] = {
val enqWidth = enq.bits.getWidth val enqWidth = enq.bits.getWidth
val quash = Wire(Bool())
require(enqWidth > 0) require(enqWidth > 0)
require(regWidth > enqWidth) require(regWidth > enqWidth)
Seq( Seq(
RegField(enqWidth, RegField(enqWidth,
RegReadFn(UInt(0)), RegReadFn(UInt(0)),
RegWriteFn((valid, data) => { RegWriteFn((valid, data) => {
enq.valid := valid enq.valid := valid && !quash
enq.bits := data enq.bits := data
Bool(true) Bool(true)
})), })),
RegField(regWidth - enqWidth - 1), RegField(regWidth - enqWidth - 1),
RegField.r(1, !enq.ready)) RegField(1,
!enq.ready,
RegWriteFn((valid, data) => {
quash := valid && data(0)
Bool(true)
})))
} }
} }