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GPIO: Make GPIO peripheral another listable one

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This commit is contained in:
Megan Wachs 2017-06-08 16:25:20 -07:00
parent 0ca609d324
commit c89f163c0d
1 changed files with 11 additions and 6 deletions
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13
src/main/scala/devices/gpio/GPIOPeriphery.scala
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@ -11,22 +11,27 @@ import rocketchip.{
} }
import uncore.tilelink2.TLFragmenter import uncore.tilelink2.TLFragmenter
case object PeripheryGPIOKey extends Field[GPIOParams] case object PeripheryGPIOKey extends Field[Seq[GPIOParams]]
trait HasPeripheryGPIO extends HasTopLevelNetworks { trait HasPeripheryGPIO extends HasTopLevelNetworks {
val gpioParams = p(PeripheryGPIOKey) val gpioParams = p(PeripheryGPIOKey)
val gpio = LazyModule(new TLGPIO(peripheryBusBytes, gpioParams)) val gpio = gpioParams map {params =>
val gpio = LazyModule(new TLGPIO(peripheryBusBytes, params))
gpio.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node) gpio.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
intBus.intnode := gpio.intnode intBus.intnode := gpio.intnode
gpio
}
} }
trait HasPeripheryGPIOBundle extends HasTopLevelNetworksBundle { trait HasPeripheryGPIOBundle extends HasTopLevelNetworksBundle {
val outer: HasPeripheryGPIO val outer: HasPeripheryGPIO
val gpio = new GPIOPortIO(outer.gpioParams) val gpio = HeterogeneousBag(outer.gpioParams(map(new GPIOPortIO(_))))
} }
trait HasPeripheryGPIOModule extends HasTopLevelNetworksModule { trait HasPeripheryGPIOModule extends HasTopLevelNetworksModule {
val outer: HasPeripheryGPIO val outer: HasPeripheryGPIO
val io: HasPeripheryGPIOBundle val io: HasPeripheryGPIOBundle
io.gpio <> outer.gpio.module.io.port (io.gpio zip outer.gpio) foreach { case (io, device) =>
io.gpio <> device.module.io.port
}
} }