riscv/sifive-blocks
1
0
Fork 0
Code Releases Activity

ShiftRegInit: use the rocket-chip version since it is there now

Browse Source
This commit is contained in:
Megan Wachs
2017-09-05 17:51:40 -07:00
parent 7d07e3af0b
commit c68d556768
4 changed files with 10 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src/main/scala/devices/spi/SPIPhysical.scala
View File

@ -2,7 +2,7 @@
package sifive.blocks.devices.spi
import Chisel._
import sifive.blocks.util.ShiftRegisterInit
import freechipchips.rocketchip.util.ShiftRegInit
class SPIMicroOp(c: SPIParamsBase) extends SPIBundle(c) {
val fn = Bits(width = 1)
@ -39,8 +39,8 @@ class SPIPhysical(c: SPIParamsBase) extends Module {
val last = Wire(init = Bool(false))
// Delayed versions
val setup_d = Reg(next = setup)
val sample_d = ShiftRegisterInit(sample, c.sampleDelay, Bool(false))
val last_d = ShiftRegisterInit(last, c.sampleDelay, Bool(false))
val sample_d = ShiftRegInit(sample, c.sampleDelay, init = Bool(false))
val last_d = ShiftRegInit(last, c.sampleDelay, init = Bool(false))
val scnt = Reg(init = UInt(0, c.countBits))
val tcnt = Reg(io.ctrl.sck.div)