riscv/sifive-blocks
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ShiftRegInit: use the rocket-chip version since it is there now

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This commit is contained in:
Megan Wachs
2017-09-05 17:51:40 -07:00
parent 7d07e3af0b
commit c68d556768
4 changed files with 10 additions and 10 deletions
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3
src/main/scala/devices/mockaon/MockAONPeriphery.scala
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@ -3,6 +3,7 @@ package sifive.blocks.devices.mockaon
import Chisel._
import freechips.rocketchip.config.Field
import freechips.rocketchip.util.SynchronizerShiftReg
import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
import freechips.rocketchip.devices.debug.HasPeripheryDebug
import freechips.rocketchip.devices.tilelink.HasPeripheryClint
@ -43,7 +44,7 @@ trait HasPeripheryMockAONModuleImp extends LazyMultiIOModuleImp with HasPeripher
outer.aon.module.reset := Bool(true)
// Synchronize the external toggle into the clint
val rtc_sync = ShiftRegister(outer.aon.module.io.rtc.asUInt.toBool, 3)
val rtc_sync = SynchronizerShiftReg(outer.aon.module.io.rtc.asUInt.toBool, 3, Some("rtc"))
val rtc_last = Reg(init = Bool(false), next=rtc_sync)
val rtc_tick = Reg(init = Bool(false), next=(rtc_sync & (~rtc_last)))