riscv/sifive-blocks
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sifive-blocks: trust diplomacy to get names right

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This commit is contained in:
Wesley W. Terpstra
2017-02-01 13:53:54 -08:00
parent 535be3e976
commit c010a1557a
3 changed files with 9 additions and 9 deletions
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6
src/main/scala/devices/pwm/PWMPeriphery.scala
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@@ -30,8 +30,8 @@ class PWMGPIOPort(c: PWMBundleConfig)(implicit p: Parameters) extends Module {
trait PeripheryPWM { trait PeripheryPWM {
this: TopNetwork { val pwmConfigs: Seq[PWMConfig] } => this: TopNetwork { val pwmConfigs: Seq[PWMConfig] } =>
val pwmDevices = (pwmConfigs.zipWithIndex) map { case (c, i) => val pwm = (pwmConfigs.zipWithIndex) map { case (c, i) =>
val pwm = LazyModule(new TLPWM(c) { override lazy val valName = Some(s"pwm$i") }) val pwm = LazyModule(new TLPWM(c))
pwm.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node) pwm.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
intBus.intnode := pwm.intnode intBus.intnode := pwm.intnode
pwm pwm
@@ -52,7 +52,7 @@ trait PeripheryPWMModule {
val outer: PeripheryPWM val outer: PeripheryPWM
val io: PeripheryPWMBundle val io: PeripheryPWMBundle
} => } =>
(io.pwms.zipWithIndex zip outer.pwmDevices) foreach { case ((io, i), device) => (io.pwms.zipWithIndex zip outer.pwm) foreach { case ((io, i), device) =>
io.port := device.module.io.gpio io.port := device.module.io.gpio
} }
} }

6
src/main/scala/devices/spi/SPIPeriphery.scala
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@@ -8,8 +8,8 @@ import rocketchip.{TopNetwork,TopNetworkModule}
trait PeripherySPI { trait PeripherySPI {
this: TopNetwork { val spiConfigs: Seq[SPIConfig] } => this: TopNetwork { val spiConfigs: Seq[SPIConfig] } =>
val spiDevices = (spiConfigs.zipWithIndex) map {case (c, i) => val spi = (spiConfigs.zipWithIndex) map {case (c, i) =>
val spi = LazyModule(new TLSPI(c) { override lazy val valName = Some(s"spi$i") } ) val spi = LazyModule(new TLSPI(c))
spi.rnode := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node) spi.rnode := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
intBus.intnode := spi.intnode intBus.intnode := spi.intnode
spi spi
@@ -28,7 +28,7 @@ trait PeripherySPIModule {
val outer: PeripherySPI val outer: PeripherySPI
val io: PeripherySPIBundle val io: PeripherySPIBundle
} => } =>
(io.spis zip outer.spiDevices).foreach { case (io, device) => (io.spis zip outer.spi).foreach { case (io, device) =>
io <> device.module.io.port io <> device.module.io.port
} }
} }

6
src/main/scala/devices/uart/UARTPeriphery.scala
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@@ -14,8 +14,8 @@ trait PeripheryUART {
this: TopNetwork { this: TopNetwork {
val uartConfigs: Seq[UARTConfig] val uartConfigs: Seq[UARTConfig]
} => } =>
val uartDevices = uartConfigs.zipWithIndex.map { case (c, i) => val uart = uartConfigs.zipWithIndex.map { case (c, i) =>
val uart = LazyModule(new UART(c) { override lazy val valName = Some(s"uart$i") } ) val uart = LazyModule(new UART(c))
uart.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node) uart.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
intBus.intnode := uart.intnode intBus.intnode := uart.intnode
uart uart
@@ -32,7 +32,7 @@ trait PeripheryUARTModule {
val outer: PeripheryUART val outer: PeripheryUART
val io: PeripheryUARTBundle val io: PeripheryUARTBundle
} => } =>
(io.uarts zip outer.uartDevices).foreach { case (io, device) => (io.uarts zip outer.uart).foreach { case (io, device) =>
io <> device.module.io.port io <> device.module.io.port
} }
} }