riscv/sifive-blocks
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sifive-blocks: trust diplomacy to get names right

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This commit is contained in:
Wesley W. Terpstra
2017-02-01 13:53:54 -08:00
parent 535be3e976
commit c010a1557a
3 changed files with 9 additions and 9 deletions
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6
src/main/scala/devices/spi/SPIPeriphery.scala
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@ -8,8 +8,8 @@ import rocketchip.{TopNetwork,TopNetworkModule}
trait PeripherySPI {
this: TopNetwork { val spiConfigs: Seq[SPIConfig] } =>
val spiDevices = (spiConfigs.zipWithIndex) map {case (c, i) =>
val spi = LazyModule(new TLSPI(c) { override lazy val valName = Some(s"spi$i") } )
val spi = (spiConfigs.zipWithIndex) map {case (c, i) =>
val spi = LazyModule(new TLSPI(c))
spi.rnode := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
intBus.intnode := spi.intnode
spi
@ -28,7 +28,7 @@ trait PeripherySPIModule {
val outer: PeripherySPI
val io: PeripherySPIBundle
} =>
(io.spis zip outer.spiDevices).foreach { case (io, device) =>
(io.spis zip outer.spi).foreach { case (io, device) =>
io <> device.module.io.port
}
}