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devices: create periphery keys for all devices

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Standardize how they are connected to the periphery bus
This commit is contained in:
Wesley W. Terpstra
2017-02-22 18:42:47 -08:00
committed by Henry Cook
parent 03be9aba67
commit baccd5ada2
23 changed files with 277 additions and 295 deletions
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18
src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala
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@ -3,25 +3,29 @@ package sifive.blocks.devices.xilinxvc707pciex1
import Chisel._
import diplomacy.LazyModule
import rocketchip.{TopNetwork,TopNetworkModule,TopNetworkBundle}
import rocketchip.{
HasTopLevelNetworks,
HasTopLevelNetworksModule,
HasTopLevelNetworksBundle
}
import uncore.tilelink2.TLWidthWidget
trait PeripheryXilinxVC707PCIeX1 extends TopNetwork {
trait HasPeripheryXilinxVC707PCIeX1 extends HasTopLevelNetworks {
val xilinxvc707pcie = LazyModule(new XilinxVC707PCIeX1)
l2.node := xilinxvc707pcie.master
l2FrontendBus.node := xilinxvc707pcie.master
xilinxvc707pcie.slave := TLWidthWidget(socBusConfig.beatBytes)(socBus.node)
xilinxvc707pcie.control := TLWidthWidget(socBusConfig.beatBytes)(socBus.node)
intBus.intnode := xilinxvc707pcie.intnode
}
trait PeripheryXilinxVC707PCIeX1Bundle extends TopNetworkBundle {
trait HasPeripheryXilinxVC707PCIeX1Bundle extends HasTopLevelNetworksBundle {
val xilinxvc707pcie = new XilinxVC707PCIeX1IO
}
trait PeripheryXilinxVC707PCIeX1Module extends TopNetworkModule {
val outer: PeripheryXilinxVC707PCIeX1
val io: PeripheryXilinxVC707PCIeX1Bundle
trait HasPeripheryXilinxVC707PCIeX1Module extends HasTopLevelNetworksModule {
val outer: HasPeripheryXilinxVC707PCIeX1
val io: HasPeripheryXilinxVC707PCIeX1Bundle
io.xilinxvc707pcie <> outer.xilinxvc707pcie.module.io.port
}