devices: create periphery keys for all devices
Standardize how they are connected to the periphery bus
This commit is contained in:
committed by
Henry Cook
parent
03be9aba67
commit
baccd5ada2
@ -5,12 +5,11 @@ import Chisel._
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import config._
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import regmapper._
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import uncore.tilelink2._
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import junctions._
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import util._
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import rocketchip.PeripheryBusConfig
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import sifive.blocks.util.{NonBlockingEnqueue, NonBlockingDequeue}
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case class UARTConfig(
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case class UARTParams(
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address: BigInt,
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dataBits: Int = 8,
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stopBits: Int = 2,
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@ -21,23 +20,23 @@ case class UARTConfig(
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nRxEntries: Int = 8)
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trait HasUARTParameters {
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val c: UARTConfig
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val uartDataBits = c.dataBits
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val uartStopBits = c.stopBits
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val uartDivisorBits = c.divisorBits
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def c: UARTParams
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def uartDataBits = c.dataBits
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def uartStopBits = c.stopBits
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def uartDivisorBits = c.divisorBits
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val uartOversample = c.oversample
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val uartOversampleFactor = 1 << uartOversample
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val uartNSamples = c.nSamples
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def uartOversample = c.oversample
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def uartOversampleFactor = 1 << uartOversample
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def uartNSamples = c.nSamples
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val uartNTxEntries = c.nTxEntries
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val uartNRxEntries = c.nRxEntries
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def uartNTxEntries = c.nTxEntries
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def uartNRxEntries = c.nRxEntries
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require(uartDivisorBits > uartOversample)
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require(uartOversampleFactor > uartNSamples)
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}
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abstract class UARTModule(val c: UARTConfig)(implicit val p: Parameters)
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abstract class UARTModule(val c: UARTParams)(implicit val p: Parameters)
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extends Module with HasUARTParameters
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class UARTPortIO extends Bundle {
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@ -45,17 +44,11 @@ class UARTPortIO extends Bundle {
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val rxd = Bool(INPUT)
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}
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trait MixUARTParameters {
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implicit val p: Parameters
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val params: UARTConfig
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val c = params
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}
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trait UARTTopBundle extends Bundle with MixUARTParameters with HasUARTParameters {
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trait HasUARTTopBundleContents extends Bundle {
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val port = new UARTPortIO
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}
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class UARTTx(c: UARTConfig)(implicit p: Parameters) extends UARTModule(c)(p) {
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class UARTTx(c: UARTParams)(implicit p: Parameters) extends UARTModule(c)(p) {
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val io = new Bundle {
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val en = Bool(INPUT)
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val in = Decoupled(Bits(width = uartDataBits)).flip
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@ -91,7 +84,7 @@ class UARTTx(c: UARTConfig)(implicit p: Parameters) extends UARTModule(c)(p) {
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}
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}
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class UARTRx(c: UARTConfig)(implicit p: Parameters) extends UARTModule(c)(p) {
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class UARTRx(c: UARTParams)(implicit p: Parameters) extends UARTModule(c)(p) {
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val io = new Bundle {
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val en = Bool(INPUT)
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val in = Bits(INPUT, 1)
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@ -116,7 +109,7 @@ class UARTRx(c: UARTConfig)(implicit p: Parameters) extends UARTModule(c)(p) {
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}
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val sample = Reg(Bits(width = uartNSamples))
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val voter = new Majority(sample.toBools.toSet)
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val voter = Majority(sample.toBools.toSet)
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when (pulse) {
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sample := Cat(sample, io.in)
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}
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@ -164,7 +157,7 @@ class UARTRx(c: UARTConfig)(implicit p: Parameters) extends UARTModule(c)(p) {
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busy := Bool(true)
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when (expire) {
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sched := Bool(true)
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when (voter.out) {
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when (voter) {
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state := s_idle
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} .otherwise {
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state := s_data
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@ -181,7 +174,7 @@ class UARTRx(c: UARTConfig)(implicit p: Parameters) extends UARTModule(c)(p) {
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state := s_idle
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valid := Bool(true)
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} .otherwise {
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shifter := Cat(voter.out, shifter >> 1)
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shifter := Cat(voter, shifter >> 1)
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sched := Bool(true)
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}
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}
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@ -198,13 +191,16 @@ class UARTInterrupts extends Bundle {
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val txwm = Bool()
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}
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trait UARTTopModule extends Module with MixUARTParameters with HasUARTParameters with HasRegMap {
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val io: UARTTopBundle
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trait HasUARTTopModuleContents extends Module with HasUARTParameters with HasRegMap {
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val io: HasUARTTopBundleContents
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implicit val p: Parameters
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def params: UARTParams
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def c = params
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val txm = Module(new UARTTx(c))
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val txm = Module(new UARTTx(params))
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val txq = Module(new Queue(txm.io.in.bits, uartNTxEntries))
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val rxm = Module(new UARTRx(c))
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val rxm = Module(new UARTRx(params))
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val rxq = Module(new Queue(rxm.io.out.bits, uartNRxEntries))
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val divinit = 542 // (62.5MHz / 115200)
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@ -262,14 +258,8 @@ trait UARTTopModule extends Module with MixUARTParameters with HasUARTParameters
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)
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}
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class Majority(in: Set[Bool]) {
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private val n = (in.size >> 1) + 1
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private val clauses = in.subsets(n).map(_.reduce(_ && _))
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val out = clauses.reduce(_ || _)
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}
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// Magic TL2 Incantation to create a TL2 Slave
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class UART(c: UARTConfig)(implicit p: Parameters)
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extends TLRegisterRouter(c.address, interrupts = 1, beatBytes = p(PeripheryBusConfig).beatBytes)(
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new TLRegBundle(c, _) with UARTTopBundle)(
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new TLRegModule(c, _, _) with UARTTopModule)
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// Magic TL2 Incantation to create a TL2 UART
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class TLUART(w: Int, c: UARTParams)(implicit p: Parameters)
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extends TLRegisterRouter(c.address, interrupts = 1, beatBytes = w)(
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new TLRegBundle(c, _) with HasUARTTopBundleContents)(
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new TLRegModule(c, _, _) with HasUARTTopModuleContents)
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