devices: create periphery keys for all devices
Standardize how they are connected to the periphery bus
This commit is contained in:
Wesley W. Terpstra
committed by
Henry Cook
Henry Cook
parent
03be9aba67
commit
baccd5ada2
@ -3,11 +3,11 @@ package sifive.blocks.devices.spi
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import Chisel._
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class SPIInnerIO(c: SPIConfigBase) extends SPILinkIO(c) {
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class SPIInnerIO(c: SPIParamsBase) extends SPILinkIO(c) {
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val lock = Bool(OUTPUT)
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}
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class SPIArbiter(c: SPIConfigBase, n: Int) extends Module {
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class SPIArbiter(c: SPIParamsBase, n: Int) extends Module {
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val io = new Bundle {
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val inner = Vec(n, new SPIInnerIO(c)).flip
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val outer = new SPILinkIO(c)
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@ -3,7 +3,7 @@ package sifive.blocks.devices.spi
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import Chisel._
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abstract class SPIBundle(val c: SPIConfigBase) extends Bundle {
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abstract class SPIBundle(val c: SPIParamsBase) extends Bundle {
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override def cloneType: SPIBundle.this.type =
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this.getClass.getConstructors.head.newInstance(c).asInstanceOf[this.type]
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}
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@ -14,7 +14,7 @@ class SPIDataIO extends Bundle {
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val oe = Bool(OUTPUT)
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}
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class SPIPortIO(c: SPIConfigBase) extends SPIBundle(c) {
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class SPIPortIO(c: SPIParamsBase) extends SPIBundle(c) {
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val sck = Bool(OUTPUT)
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val dq = Vec(4, new SPIDataIO)
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val cs = Vec(c.csWidth, Bool(OUTPUT))
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@ -26,7 +26,7 @@ trait HasSPIProtocol {
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trait HasSPIEndian {
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val endian = Bits(width = SPIEndian.width)
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}
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class SPIFormat(c: SPIConfigBase) extends SPIBundle(c)
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class SPIFormat(c: SPIParamsBase) extends SPIBundle(c)
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with HasSPIProtocol
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with HasSPIEndian {
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val iodir = Bits(width = SPIDirection.width)
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@ -36,13 +36,13 @@ trait HasSPILength extends SPIBundle {
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val len = UInt(width = c.lengthBits)
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}
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class SPIClocking(c: SPIConfigBase) extends SPIBundle(c) {
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class SPIClocking(c: SPIParamsBase) extends SPIBundle(c) {
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val div = UInt(width = c.divisorBits)
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val pol = Bool()
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val pha = Bool()
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}
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class SPIChipSelect(c: SPIConfigBase) extends SPIBundle(c) {
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class SPIChipSelect(c: SPIParamsBase) extends SPIBundle(c) {
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val id = UInt(width = c.csIdBits)
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val dflt = Vec(c.csWidth, Bool())
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@ -57,19 +57,19 @@ trait HasSPICSMode {
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val mode = Bits(width = SPICSMode.width)
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}
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class SPIDelay(c: SPIConfigBase) extends SPIBundle(c) {
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class SPIDelay(c: SPIParamsBase) extends SPIBundle(c) {
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val cssck = UInt(width = c.delayBits)
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val sckcs = UInt(width = c.delayBits)
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val intercs = UInt(width = c.delayBits)
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val interxfr = UInt(width = c.delayBits)
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}
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class SPIWatermark(c: SPIConfigBase) extends SPIBundle(c) {
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class SPIWatermark(c: SPIParamsBase) extends SPIBundle(c) {
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val tx = UInt(width = c.txDepthBits)
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val rx = UInt(width = c.rxDepthBits)
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}
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class SPIControl(c: SPIConfigBase) extends SPIBundle(c) {
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class SPIControl(c: SPIParamsBase) extends SPIBundle(c) {
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val fmt = new SPIFormat(c) with HasSPILength
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val sck = new SPIClocking(c)
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val cs = new SPIChipSelect(c) with HasSPICSMode
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@ -78,7 +78,7 @@ class SPIControl(c: SPIConfigBase) extends SPIBundle(c) {
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}
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object SPIControl {
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def init(c: SPIConfigBase): SPIControl = {
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def init(c: SPIParamsBase): SPIControl = {
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val ctrl = Wire(new SPIControl(c))
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ctrl.fmt.proto := SPIProtocol.Single
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ctrl.fmt.iodir := SPIDirection.Rx
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@ -3,13 +3,13 @@ package sifive.blocks.devices.spi
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import Chisel._
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class SPIFIFOControl(c: SPIConfigBase) extends SPIBundle(c) {
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class SPIFIFOControl(c: SPIParamsBase) extends SPIBundle(c) {
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val fmt = new SPIFormat(c) with HasSPILength
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val cs = new Bundle with HasSPICSMode
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val wm = new SPIWatermark(c)
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}
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class SPIFIFO(c: SPIConfigBase) extends Module {
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class SPIFIFO(c: SPIParamsBase) extends Module {
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val io = new Bundle {
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val ctrl = new SPIFIFOControl(c).asInput
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val link = new SPIInnerIO(c)
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@ -3,7 +3,7 @@ package sifive.blocks.devices.spi
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import Chisel._
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class SPIFlashInsn(c: SPIFlashConfigBase) extends SPIBundle(c) {
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class SPIFlashInsn(c: SPIFlashParamsBase) extends SPIBundle(c) {
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val cmd = new Bundle with HasSPIProtocol {
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val code = Bits(width = c.insnCmdBits)
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val en = Bool()
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@ -18,13 +18,13 @@ class SPIFlashInsn(c: SPIFlashConfigBase) extends SPIBundle(c) {
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val data = new Bundle with HasSPIProtocol
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}
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class SPIFlashControl(c: SPIFlashConfigBase) extends SPIBundle(c) {
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class SPIFlashControl(c: SPIFlashParamsBase) extends SPIBundle(c) {
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val insn = new SPIFlashInsn(c)
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val fmt = new Bundle with HasSPIEndian
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}
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object SPIFlashInsn {
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def init(c: SPIFlashConfigBase): SPIFlashInsn = {
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def init(c: SPIFlashParamsBase): SPIFlashInsn = {
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val insn = Wire(new SPIFlashInsn(c))
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insn.cmd.en := Bool(true)
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insn.cmd.code := Bits(0x03)
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@ -38,12 +38,12 @@ object SPIFlashInsn {
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}
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}
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class SPIFlashAddr(c: SPIFlashConfigBase) extends SPIBundle(c) {
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class SPIFlashAddr(c: SPIFlashParamsBase) extends SPIBundle(c) {
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val next = UInt(width = c.insnAddrBits)
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val hold = UInt(width = c.insnAddrBits)
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}
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class SPIFlashMap(c: SPIFlashConfigBase) extends Module {
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class SPIFlashMap(c: SPIFlashParamsBase) extends Module {
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val io = new Bundle {
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val en = Bool(INPUT)
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val ctrl = new SPIFlashControl(c).asInput
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@ -3,7 +3,7 @@ package sifive.blocks.devices.spi
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import Chisel._
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class SPILinkIO(c: SPIConfigBase) extends SPIBundle(c) {
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class SPILinkIO(c: SPIParamsBase) extends SPIBundle(c) {
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val tx = Decoupled(Bits(width = c.frameBits))
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val rx = Valid(Bits(width = c.frameBits)).flip
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@ -17,7 +17,7 @@ class SPILinkIO(c: SPIConfigBase) extends SPIBundle(c) {
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val active = Bool(INPUT)
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}
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class SPIMedia(c: SPIConfigBase) extends Module {
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class SPIMedia(c: SPIParamsBase) extends Module {
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val io = new Bundle {
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val port = new SPIPortIO(c)
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val ctrl = new Bundle {
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@ -2,56 +2,58 @@
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package sifive.blocks.devices.spi
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import Chisel._
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import config.Field
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import diplomacy.LazyModule
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import uncore.tilelink2._
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import rocketchip.{TopNetwork,TopNetworkModule}
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import rocketchip.{
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HasTopLevelNetworks,
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HasTopLevelNetworksBundle,
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HasTopLevelNetworksModule
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}
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import uncore.tilelink2.{TLFragmenter, TLWidthWidget}
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import util.HeterogeneousBag
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trait PeripherySPI {
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this: TopNetwork { val spiConfigs: Seq[SPIConfig] } =>
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val spi = (spiConfigs.zipWithIndex) map {case (c, i) =>
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val spi = LazyModule(new TLSPI(c))
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spi.rnode := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
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case object PeripherySPIKey extends Field[Seq[SPIParams]]
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trait HasPeripherySPI extends HasTopLevelNetworks {
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val spiParams = p(PeripherySPIKey)
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val spis = spiParams map { params =>
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val spi = LazyModule(new TLSPI(peripheryBusBytes, params))
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spi.rnode := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
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intBus.intnode := spi.intnode
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spi
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}
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}
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trait PeripherySPIBundle {
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this: { val spiConfigs: Seq[SPIConfig] } =>
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val spis = HeterogeneousBag(spiConfigs.map(new SPIPortIO(_)))
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trait HasPeripherySPIBundle extends HasTopLevelNetworksBundle {
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val outer: HasPeripherySPI
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val spis = HeterogeneousBag(outer.spiParams.map(new SPIPortIO(_)))
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}
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trait PeripherySPIModule {
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this: TopNetworkModule {
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val spiConfigs: Seq[SPIConfig]
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val outer: PeripherySPI
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val io: PeripherySPIBundle
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} =>
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(io.spis zip outer.spi).foreach { case (io, device) =>
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trait HasPeripherySPIModule extends HasTopLevelNetworksModule {
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val outer: HasPeripherySPI
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val io: HasPeripherySPIBundle
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(io.spis zip outer.spis).foreach { case (io, device) =>
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io <> device.module.io.port
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}
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}
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case object PeripherySPIFlashKey extends Field[SPIFlashParams]
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trait PeripherySPIFlash {
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this: TopNetwork { val spiFlashConfig: SPIFlashConfig } =>
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val qspi = LazyModule(new TLSPIFlash(spiFlashConfig))
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qspi.rnode := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
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qspi.fnode := TLFragmenter(1, cacheBlockBytes)(TLWidthWidget(peripheryBusConfig.beatBytes)(peripheryBus.node))
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trait HasPeripherySPIFlash extends HasTopLevelNetworks {
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val spiFlashParams = p(PeripherySPIFlashKey)
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val qspi = LazyModule(new TLSPIFlash(peripheryBusBytes, spiFlashParams))
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qspi.rnode := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
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qspi.fnode := TLFragmenter(1, cacheBlockBytes)(TLWidthWidget(peripheryBusBytes)(peripheryBus.node))
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intBus.intnode := qspi.intnode
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}
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trait PeripherySPIFlashBundle {
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this: { val spiFlashConfig: SPIFlashConfig } =>
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val qspi = new SPIPortIO(spiFlashConfig)
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trait HasPeripherySPIFlashBundle extends HasTopLevelNetworksBundle {
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val outer: HasPeripherySPIFlash
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val qspi = new SPIPortIO(outer.spiFlashParams)
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}
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trait PeripherySPIFlashModule {
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this: TopNetworkModule {
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val spiConfigs: Seq[SPIConfig]
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val outer: PeripherySPIFlash
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val io: PeripherySPIFlashBundle
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} =>
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trait HasPeripherySPIFlashModule extends HasTopLevelNetworksModule {
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val outer: HasPeripherySPIFlash
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val io: HasPeripherySPIFlashBundle
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io.qspi <> outer.qspi.module.io.port
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}
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@ -4,7 +4,7 @@ package sifive.blocks.devices.spi
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import Chisel._
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import sifive.blocks.util.ShiftRegisterInit
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class SPIMicroOp(c: SPIConfigBase) extends SPIBundle(c) {
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class SPIMicroOp(c: SPIParamsBase) extends SPIBundle(c) {
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val fn = Bits(width = 1)
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val stb = Bool()
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val cnt = UInt(width = c.countBits)
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@ -16,12 +16,12 @@ object SPIMicroOp {
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def Delay = UInt(1, 1)
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}
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class SPIPhyControl(c: SPIConfigBase) extends SPIBundle(c) {
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class SPIPhyControl(c: SPIParamsBase) extends SPIBundle(c) {
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val sck = new SPIClocking(c)
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val fmt = new SPIFormat(c)
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}
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class SPIPhysical(c: SPIConfigBase) extends Module {
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class SPIPhysical(c: SPIParamsBase) extends Module {
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val io = new SPIBundle(c) {
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val port = new SPIPortIO(c)
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val ctrl = new SPIPhyControl(c).asInput
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@ -4,13 +4,13 @@ package sifive.blocks.devices.spi
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import Chisel._
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import sifive.blocks.devices.gpio.{GPIOPin, GPIOOutputPinCtrl, GPIOInputPinCtrl}
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class SPIPinsIO(c: SPIConfigBase) extends SPIBundle(c) {
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class SPIPinsIO(c: SPIParamsBase) extends SPIBundle(c) {
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val sck = new GPIOPin
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val dq = Vec(4, new GPIOPin)
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val cs = Vec(c.csWidth, new GPIOPin)
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}
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class SPIGPIOPort(c: SPIConfigBase, syncStages: Int = 0, driveStrength: Bool = Bool(false)) extends Module {
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class SPIGPIOPort(c: SPIParamsBase, syncStages: Int = 0, driveStrength: Bool = Bool(false)) extends Module {
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val io = new SPIBundle(c) {
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val spi = new SPIPortIO(c).flip
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val pins = new SPIPinsIO(c)
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@ -3,14 +3,13 @@ package sifive.blocks.devices.spi
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import Chisel._
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import config._
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import uncore.tilelink2._
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import diplomacy._
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import regmapper._
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import junctions._
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import rocketchip.PeripheryBusConfig
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import uncore.tilelink2._
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import sifive.blocks.util.{NonBlockingEnqueue, NonBlockingDequeue}
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trait SPIConfigBase {
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trait SPIParamsBase {
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val rAddress: BigInt
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val rSize: BigInt
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val rxDepth: Int
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@ -32,7 +31,7 @@ trait SPIConfigBase {
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}
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case class SPIConfig(
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case class SPIParams(
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rAddress: BigInt,
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rSize: BigInt = 0x1000,
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rxDepth: Int = 8,
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@ -42,15 +41,15 @@ case class SPIConfig(
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delayBits: Int = 8,
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divisorBits: Int = 12,
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sampleDelay: Int = 2)
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extends SPIConfigBase {
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extends SPIParamsBase {
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require(frameBits >= 4)
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require(sampleDelay >= 0)
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}
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class SPITopBundle(val i: Vec[Vec[Bool]], val r: Vec[TLBundle]) extends Bundle
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class SPITopBundle(val i: util.HeterogeneousBag[Vec[Bool]], val r: util.HeterogeneousBag[TLBundle]) extends Bundle
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class SPITopModule[B <: SPITopBundle](c: SPIConfigBase, bundle: => B, outer: TLSPIBase)
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class SPITopModule[B <: SPITopBundle](c: SPIParamsBase, bundle: => B, outer: TLSPIBase)
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extends LazyModuleImp(outer) {
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val io = new Bundle {
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@ -108,13 +107,13 @@ class SPITopModule[B <: SPITopBundle](c: SPIConfigBase, bundle: => B, outer: TLS
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RegField.r(1, ip.rxwm)))
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}
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abstract class TLSPIBase(c: SPIConfigBase)(implicit p: Parameters) extends LazyModule {
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abstract class TLSPIBase(w: Int, c: SPIParamsBase)(implicit p: Parameters) extends LazyModule {
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require(isPow2(c.rSize))
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val rnode = TLRegisterNode(address = AddressSet(c.rAddress, c.rSize-1), beatBytes = p(PeripheryBusConfig).beatBytes)
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val rnode = TLRegisterNode(address = AddressSet(c.rAddress, c.rSize-1), beatBytes = w)
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val intnode = IntSourceNode(1)
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}
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class TLSPI(c: SPIConfig)(implicit p: Parameters) extends TLSPIBase(c)(p) {
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class TLSPI(w: Int, c: SPIParams)(implicit p: Parameters) extends TLSPIBase(w,c)(p) {
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lazy val module = new SPITopModule(c, new SPITopBundle(intnode.bundleOut, rnode.bundleIn), this) {
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mac.io.link <> fifo.io.link
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rnode.regmap(regmapBase:_*)
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@ -7,7 +7,7 @@ import diplomacy._
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import regmapper._
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import uncore.tilelink2._
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trait SPIFlashConfigBase extends SPIConfigBase {
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trait SPIFlashParamsBase extends SPIParamsBase {
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val fAddress: BigInt
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val fSize: BigInt
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@ -18,7 +18,7 @@ trait SPIFlashConfigBase extends SPIConfigBase {
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lazy val insnAddrLenBits = log2Floor(insnAddrBytes) + 1
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}
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case class SPIFlashConfig(
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case class SPIFlashParams(
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rAddress: BigInt,
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fAddress: BigInt,
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rSize: BigInt = 0x1000,
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@ -29,7 +29,7 @@ case class SPIFlashConfig(
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delayBits: Int = 8,
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divisorBits: Int = 12,
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sampleDelay: Int = 2)
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extends SPIFlashConfigBase {
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extends SPIFlashParamsBase {
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val frameBits = 8
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val insnAddrBytes = 4
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val insnPadLenBits = 4
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@ -38,10 +38,10 @@ case class SPIFlashConfig(
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require(sampleDelay >= 0)
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}
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class SPIFlashTopBundle(i: Vec[Vec[Bool]], r: Vec[TLBundle], val f: Vec[TLBundle]) extends SPITopBundle(i, r)
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class SPIFlashTopBundle(i: util.HeterogeneousBag[Vec[Bool]], r: util.HeterogeneousBag[TLBundle], val f: util.HeterogeneousBag[TLBundle]) extends SPITopBundle(i, r)
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class SPIFlashTopModule[B <: SPIFlashTopBundle]
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(c: SPIFlashConfigBase, bundle: => B, outer: TLSPIFlashBase)
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(c: SPIFlashParamsBase, bundle: => B, outer: TLSPIFlashBase)
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extends SPITopModule(c, bundle, outer) {
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val flash = Module(new SPIFlashMap(c))
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@ -91,7 +91,7 @@ class SPIFlashTopModule[B <: SPIFlashTopBundle]
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SPICRs.insnpad -> Seq(RegField(c.frameBits, insn.pad.code)))
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}
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abstract class TLSPIFlashBase(c: SPIFlashConfigBase)(implicit p: Parameters) extends TLSPIBase(c)(p) {
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abstract class TLSPIFlashBase(w: Int, c: SPIFlashParamsBase)(implicit p: Parameters) extends TLSPIBase(w,c)(p) {
|
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require(isPow2(c.fSize))
|
||||
val fnode = TLManagerNode(1, TLManagerParameters(
|
||||
address = Seq(AddressSet(c.fAddress, c.fSize-1)),
|
||||
@ -101,7 +101,7 @@ abstract class TLSPIFlashBase(c: SPIFlashConfigBase)(implicit p: Parameters) ext
|
||||
fifoId = Some(0)))
|
||||
}
|
||||
|
||||
class TLSPIFlash(c: SPIFlashConfig)(implicit p: Parameters) extends TLSPIFlashBase(c)(p) {
|
||||
class TLSPIFlash(w: Int, c: SPIFlashParams)(implicit p: Parameters) extends TLSPIFlashBase(w,c)(p) {
|
||||
lazy val module = new SPIFlashTopModule(c,
|
||||
new SPIFlashTopBundle(intnode.bundleOut, rnode.bundleIn, fnode.bundleIn), this) {
|
||||
|
||||
|
||||
Reference in New Issue
Block a user