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devices: create periphery keys for all devices

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Standardize how they are connected to the periphery bus
This commit is contained in:
Wesley W. Terpstra
2017-02-22 18:42:47 -08:00
committed by Henry Cook
parent 03be9aba67
commit baccd5ada2
23 changed files with 277 additions and 295 deletions
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35
src/main/scala/devices/pwm/PWM.scala
View File

@ -3,9 +3,8 @@ package sifive.blocks.devices.pwm
import Chisel._
import Chisel.ImplicitConversions._
import config._
import config.Parameters
import regmapper._
import rocketchip.PeripheryBusConfig
import uncore.tilelink2._
import util._
@ -13,7 +12,7 @@ import sifive.blocks.util.GenericTimer
// Core PWM Functionality & Register Interface
class PWM(val ncmp: Int = 4, val cmpWidth: Int = 16)(implicit p: Parameters) extends GenericTimer {
class PWM(val ncmp: Int = 4, val cmpWidth: Int = 16) extends GenericTimer {
protected def countWidth = ((1 << scaleWidth) - 1) + cmpWidth
protected lazy val countAlways = RegEnable(io.regs.cfg.write.bits(12), Bool(false), io.regs.cfg.write.valid && unlocked)
protected lazy val feed = count.carryOut(scale + UInt(cmpWidth))
@ -38,35 +37,31 @@ class PWM(val ncmp: Int = 4, val cmpWidth: Int = 16)(implicit p: Parameters) ext
countEn := countAlways || oneShot
}
case class PWMConfig(
case class PWMParams(
address: BigInt,
size: Int = 0x1000,
regBytes: Int = 4,
ncmp: Int = 4,
cmpWidth: Int = 16)
trait HasPWMParameters {
implicit val p: Parameters
val params: PWMConfig
val c = params
trait HasPWMBundleContents extends Bundle {
val params: PWMParams
val gpio = Vec(params.ncmp, Bool()).asOutput
}
trait PWMBundle extends Bundle with HasPWMParameters {
val gpio = Vec(c.ncmp, Bool()).asOutput
}
trait HasPWMModuleContents extends Module with HasRegMap {
val io: HasPWMBundleContents
val params: PWMParams
trait PWMModule extends Module with HasRegMap with HasPWMParameters {
val io: PWMBundle
val pwm = Module(new PWM(c.ncmp, c.cmpWidth))
val pwm = Module(new PWM(params.ncmp, params.cmpWidth))
interrupts := pwm.io.ip
io.gpio := pwm.io.gpio
regmap((GenericTimer.timerRegMap(pwm, 0, c.regBytes)):_*)
regmap((GenericTimer.timerRegMap(pwm, 0, params.regBytes)):_*)
}
class TLPWM(c: PWMConfig)(implicit p: Parameters)
extends TLRegisterRouter(c.address, interrupts = c.ncmp, size = c.size, beatBytes = p(PeripheryBusConfig).beatBytes)(
new TLRegBundle(c, _) with PWMBundle)(
new TLRegModule(c, _, _) with PWMModule)
class TLPWM(w: Int, c: PWMParams)(implicit p: Parameters)
extends TLRegisterRouter(c.address, interrupts = c.ncmp, size = c.size, beatBytes = w)(
new TLRegBundle(c, _) with HasPWMBundleContents)(
new TLRegModule(c, _, _) with HasPWMModuleContents)

45
src/main/scala/devices/pwm/PWMPeriphery.scala
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@ -2,24 +2,28 @@
package sifive.blocks.devices.pwm
import Chisel._
import config._
import config.Field
import diplomacy.LazyModule
import rocketchip.{TopNetwork,TopNetworkModule}
import rocketchip.{
HasTopLevelNetworks,
HasTopLevelNetworksBundle,
HasTopLevelNetworksModule
}
import uncore.tilelink2.TLFragmenter
import util.HeterogeneousBag
import sifive.blocks.devices.gpio._
class PWMPortIO(c: PWMConfig)(implicit p: Parameters) extends Bundle {
class PWMPortIO(c: PWMParams) extends Bundle {
val port = Vec(c.ncmp, Bool()).asOutput
override def cloneType: this.type = new PWMPortIO(c).asInstanceOf[this.type]
}
class PWMPinsIO(c: PWMConfig)(implicit p: Parameters) extends Bundle {
class PWMPinsIO(c: PWMParams) extends Bundle {
val pwm = Vec(c.ncmp, new GPIOPin)
}
class PWMGPIOPort(c: PWMConfig)(implicit p: Parameters) extends Module {
class PWMGPIOPort(c: PWMParams) extends Module {
val io = new Bundle {
val pwm = new PWMPortIO(c).flip()
val pins = new PWMPinsIO(c)
@ -28,31 +32,28 @@ class PWMGPIOPort(c: PWMConfig)(implicit p: Parameters) extends Module {
GPIOOutputPinCtrl(io.pins.pwm, io.pwm.port.asUInt)
}
trait PeripheryPWM {
this: TopNetwork { val pwmConfigs: Seq[PWMConfig] } =>
case object PeripheryPWMKey extends Field[Seq[PWMParams]]
val pwm = (pwmConfigs.zipWithIndex) map { case (c, i) =>
val pwm = LazyModule(new TLPWM(c))
pwm.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
trait HasPeripheryPWM extends HasTopLevelNetworks {
val pwmParams = p(PeripheryPWMKey)
val pwms = pwmParams map { params =>
val pwm = LazyModule(new TLPWM(peripheryBusBytes, params))
pwm.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
intBus.intnode := pwm.intnode
pwm
}
}
trait PeripheryPWMBundle {
this: {
val p: Parameters
val pwmConfigs: Seq[PWMConfig]
} =>
val pwms = HeterogeneousBag(pwmConfigs.map(new PWMPortIO(_)(p)))
trait HasPeripheryPWMBundle extends HasTopLevelNetworksBundle {
val outer: HasPeripheryPWM
val pwms = HeterogeneousBag(outer.pwmParams.map(new PWMPortIO(_)))
}
trait PeripheryPWMModule {
this: TopNetworkModule {
val outer: PeripheryPWM
val io: PeripheryPWMBundle
} =>
(io.pwms.zipWithIndex zip outer.pwm) foreach { case ((io, i), device) =>
trait HasPeripheryPWMModule extends HasTopLevelNetworksModule {
val outer: HasPeripheryPWM
val io: HasPeripheryPWMBundle
(io.pwms zip outer.pwms) foreach { case (io, device) =>
io.port := device.module.io.gpio
}
}