devices: create periphery keys for all devices

Standardize how they are connected to the periphery bus

src/main/scala/devices/mockaon/MockAON.scala

@@ -5,13 +5,12 @@ import Chisel._
 import config._
 import regmapper._
 import uncore.tilelink2._
-import rocketchip.PeripheryBusConfig
 
 import sifive.blocks.util.GenericTimer
 
-case class MockAONConfig(
-  address: BigInt = BigInt(0x10000000),
-  nBackupRegs: Int = 16) {
+case class MockAONParams(
+    address: BigInt = BigInt(0x10000000),
+    nBackupRegs: Int = 16) {
   def size: Int = 0x1000
   def regBytes: Int = 4
   def wdogOffset: Int = 0
@@ -20,12 +19,6 @@ case class MockAONConfig(
   def pmuOffset: Int = 0x100
 }
 
-trait HasMockAONParameters {
-  implicit val p: Parameters
-  val params: MockAONConfig
-  val c = params
-}
-
 class MockAONPMUIO extends Bundle {
   val vddpaden = Bool(OUTPUT)
   val dwakeup = Bool(INPUT)
@@ -36,10 +29,10 @@ class MockAONMOffRstIO extends Bundle {
   val corerst = Bool(OUTPUT)
 }
 
-trait MockAONBundle extends Bundle with HasMockAONParameters {
+trait HasMockAONBundleContents extends Bundle {
 
   // Output of the Power Management Sequencer
-  val moff = new MockAONMOffRstIO ()
+  val moff = new MockAONMOffRstIO
 
   // This goes out to wrapper
   // to be combined to create aon_rst.
@@ -56,8 +49,10 @@ trait MockAONBundle extends Bundle with HasMockAONParameters {
   val resetCauses = new ResetCauses().asInput
 }
 
-trait MockAONModule extends Module with HasRegMap with HasMockAONParameters {
-  val io: MockAONBundle
+trait HasMockAONModuleContents extends Module with HasRegMap {
+  val io: HasMockAONBundleContents
+  val params: MockAONParams
+  val c = params
 
   // the expectation here is that Chisel's implicit reset is aonrst,
   // which is asynchronous, so don't use synchronous-reset registers.
@@ -99,7 +94,7 @@ trait MockAONModule extends Module with HasRegMap with HasMockAONParameters {
 
 }
 
-class MockAON(c: MockAONConfig)(implicit p: Parameters)
-  extends TLRegisterRouter(c.address, interrupts = 2, size = c.size, beatBytes = p(PeripheryBusConfig).beatBytes, concurrency = 1)(
-  new TLRegBundle(c, _)    with MockAONBundle)(
-  new TLRegModule(c, _, _) with MockAONModule)
+class TLMockAON(w: Int, c: MockAONParams)(implicit p: Parameters)
+  extends TLRegisterRouter(c.address, interrupts = 2, size = c.size, beatBytes = w, concurrency = 1)(
+  new TLRegBundle(c, _)    with HasMockAONBundleContents)(
+  new TLRegModule(c, _, _) with HasMockAONModuleContents)

src/main/scala/devices/mockaon/MockAONPeriphery.scala

@@ -2,33 +2,38 @@
 package sifive.blocks.devices.mockaon
 
 import Chisel._
+import config.Field
+import coreplex.CoreplexRISCVPlatform
 import diplomacy.LazyModule
-import rocketchip.{TopNetwork,TopNetworkModule}
+import rocketchip.{
+  HasTopLevelNetworks,
+  HasTopLevelNetworksBundle,
+  HasTopLevelNetworksModule
+}
 import uncore.tilelink2.{IntXing, TLAsyncCrossingSource, TLFragmenter}
-import coreplex._
 
-trait PeripheryMockAON extends TopNetwork {
-  val mockAONConfig: MockAONConfig
+case object PeripheryMockAONKey extends Field[MockAONParams]
+
+trait HasPeripheryMockAON extends HasTopLevelNetworks {
   val coreplex: CoreplexRISCVPlatform
 
   // We override the clock & Reset here so that all synchronizers, etc
   // are in the proper clock domain.
-  val aon = LazyModule(new MockAONWrapper(mockAONConfig))
+  val mockAONParams= p(PeripheryMockAONKey)
+  val aon = LazyModule(new MockAONWrapper(peripheryBusBytes, mockAONParams))
   val aon_int = LazyModule(new IntXing)
-  aon.node := TLAsyncCrossingSource()(TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node))
+  aon.node := TLAsyncCrossingSource()(TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node))
   aon_int.intnode := aon.intnode
   intBus.intnode := aon_int.intnode
 }
 
-trait PeripheryMockAONBundle {
+trait HasPeripheryMockAONBundle extends HasTopLevelNetworksBundle {
   val aon = new MockAONWrapperBundle()
 }
 
-trait PeripheryMockAONModule {
-  this: TopNetworkModule {
-    val outer: PeripheryMockAON
-    val io: PeripheryMockAONBundle
-  } =>
+trait HasPeripheryMockAONModule extends HasTopLevelNetworksModule {
+  val outer: HasPeripheryMockAON
+  val io: HasPeripheryMockAONBundle
 
   io.aon <> outer.aon.module.io
 

src/main/scala/devices/mockaon/MockAONWrapper.scala

@@ -27,11 +27,11 @@ class MockAONWrapperBundle extends Bundle {
   val rsts = new MockAONMOffRstIO()
 }
 
-class MockAONWrapper(c: MockAONConfig)(implicit p: Parameters) extends LazyModule {
+class MockAONWrapper(w: Int, c: MockAONParams)(implicit p: Parameters) extends LazyModule {
 
   val node = TLAsyncInputNode()
   val intnode = IntOutputNode()
-  val aon = LazyModule (new MockAON(c)(p))
+  val aon = LazyModule(new TLMockAON(w, c))
 
   // We only need to isolate the signals
   // coming from MOFF to AON,