UART: actually return the pins, not just the module. We should do this for the other peripherals as well
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@ -29,10 +29,10 @@ trait HasPeripheryUARTBundle {
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uarts.foreach { _.rxd := UInt(1) }
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}
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def UARTtoGPIOPins(syncStages: Int = 0): Seq[UARTGPIOPort] = uarts.map { u =>
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def UARTtoGPIOPins(syncStages: Int = 0): Seq[UARTPinsIO] = uarts.map { u =>
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val pin = Module(new UARTGPIOPort(syncStages))
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pin.io.uart <> u
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pin
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pin.io.pins
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}
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}
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