riscv/sifive-blocks
1
0
Fork 0
Code Releases Activity

UART: actually return the pins, not just the module. We should do this for the other peripherals as well

Browse Source
This commit is contained in:
Megan Wachs 2017-06-12 18:08:35 -07:00
parent b06b80dccd
commit b3f656affe
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/main/scala/devices/uart/UARTPeriphery.scala
View File

@ -29,10 +29,10 @@ trait HasPeripheryUARTBundle {
uarts.foreach { _.rxd := UInt(1) } uarts.foreach { _.rxd := UInt(1) }
} }
def UARTtoGPIOPins(syncStages: Int = 0): Seq[UARTGPIOPort] = uarts.map { u => def UARTtoGPIOPins(syncStages: Int = 0): Seq[UARTPinsIO] = uarts.map { u =>
val pin = Module(new UARTGPIOPort(syncStages)) val pin = Module(new UARTGPIOPort(syncStages))
pin.io.uart <> u pin.io.uart <> u
pin pin.io.pins
} }
} }