UART: actually return the pins, not just the module. We should do this for the other peripherals as well
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		| @@ -29,10 +29,10 @@ trait HasPeripheryUARTBundle { | ||||
|     uarts.foreach { _.rxd := UInt(1) } | ||||
|   } | ||||
|  | ||||
|   def UARTtoGPIOPins(syncStages: Int = 0): Seq[UARTGPIOPort] = uarts.map { u => | ||||
|   def UARTtoGPIOPins(syncStages: Int = 0): Seq[UARTPinsIO] = uarts.map { u => | ||||
|     val pin = Module(new UARTGPIOPort(syncStages)) | ||||
|     pin.io.uart <> u | ||||
|     pin | ||||
|     pin.io.pins | ||||
|   } | ||||
| } | ||||
|  | ||||
|   | ||||
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