riscv/sifive-blocks
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remove duplicate ResetCatchAndSync definition

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This commit is contained in:
Megan Wachs 2017-08-24 18:12:36 -07:00
parent 402017d34e
commit acb8889382
2 changed files with 1 additions and 43 deletions
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2
src/main/scala/devices/mockaon/MockAONWrapper.scala
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@ -7,7 +7,7 @@ import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
import sifive.blocks.devices.pinctrl.{EnhancedPin}
import sifive.blocks.util.{DeglitchShiftRegister, ResetCatchAndSync}
import sifive.blocks.util.{DeglitchShiftRegister}
/* The wrapper handles the Clock and Reset Generation for The AON block itself,
and instantiates real pad controls (aka pull-ups)*/

42
src/main/scala/util/ResetCatchAndSync.scala
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@ -1,42 +0,0 @@
// See LICENSE for license details.
package sifive.blocks.util
import Chisel._
import freechips.rocketchip.util.AsyncResetRegVec
/** Reset: asynchronous assert,
* synchronous de-assert
*
*/
class ResetCatchAndSync (sync: Int = 3) extends Module {
val io = new Bundle {
val sync_reset = Bool(OUTPUT)
}
val reset_n_catch_reg = Module (new AsyncResetRegVec(sync, 0))
reset_n_catch_reg.io.en := Bool(true)
reset_n_catch_reg.io.d := Cat(Bool(true), reset_n_catch_reg.io.q >> 1)
io.sync_reset := ~reset_n_catch_reg.io.q(0)
}
object ResetCatchAndSync {
def apply(clk: Clock, rst: Bool, sync: Int = 3, name: Option[String] = None): Bool = {
val catcher = Module (new ResetCatchAndSync(sync))
if (name.isDefined) {catcher.suggestName(name.get)}
catcher.clock := clk
catcher.reset := rst
catcher.io.sync_reset
}
def apply(clk: Clock, rst: Bool, sync: Int, name: String): Bool = apply(clk, rst, sync, Some(name))
def apply(clk: Clock, rst: Bool, name: String): Bool = apply(clk, rst, name = Some(name))
}