Ports: Rename the 'fromXYZPort' to 'fromPort' since it's redundant

src/main/scala/devices/gpio/GPIOPins.scala

@@ -16,7 +16,7 @@ class GPIOPins[T <: Pin] (pingen: ()=> T,  c: GPIOParams) extends Bundle {
   override def cloneType: this.type =
     this.getClass.getConstructors.head.newInstance(pingen, c).asInstanceOf[this.type]
 
-  def fromGPIOPort(port: GPIOPortIO){
+  def fromPort(port: GPIOPortIO){
 
     // This will just match up the components of the Bundle that
     // exist in both.

src/main/scala/devices/i2c/I2CPins.scala

@@ -15,7 +15,7 @@ class I2CPins[T <: Pin](pingen: () => T) extends Bundle {
   override def cloneType: this.type =
     this.getClass.getConstructors.head.newInstance(pingen).asInstanceOf[this.type]
 
-  def fromI2CPort(i2c: I2CPort, clock: Clock, reset: Bool, syncStages: Int = 0) = {
+  def fromPort(i2c: I2CPort, clock: Clock, reset: Bool, syncStages: Int = 0) = {
     withClockAndReset(clock, reset) {
       scl.outputPin(i2c.scl.out, pue=true.B, ie = true.B)
       scl.o.oe := i2c.scl.oe

src/main/scala/devices/jtag/JTAGPins.scala

@@ -1,13 +1,12 @@
 // See LICENSE for license details.
-package sifive.blocks.devices.gpio
+package sifive.blocks.devices.jtag
 
 import Chisel._
 
 // ------------------------------------------------------------
-// SPI, UART, etc are with their
-// respective packages,
-// This file is for those that don't seem to have a good place
-// to put them otherwise.
+// SPI, UART, etc are with their respective packages,
+// JTAG doesn't really correspond directly to a device, but it does
+// define pins as those devices do.
 // ------------------------------------------------------------
 
 import freechips.rocketchip.config._
@@ -22,7 +21,7 @@ class JTAGPins[T <: Pin](pingen: () => T, hasTRSTn: Boolean = true) extends Bund
   val TDO        = pingen()
   val TRSTn = if (hasTRSTn) Option(pingen()) else None
 
-  def fromJTAGPort(jtag: JTAGIO): Unit = {
+  def fromPort(jtag: JTAGIO): Unit = {
     jtag.TCK  := TCK.inputPin (pue = Bool(true)).asClock
     jtag.TMS  := TMS.inputPin (pue = Bool(true))
     jtag.TDI  := TDI.inputPin(pue = Bool(true))

src/main/scala/devices/pwm/PWMPeriphery.scala

@@ -20,7 +20,7 @@ class PWMPins[T <: Pin] (pingen: ()=> T, val c: PWMParams) extends Bundle {
   override def cloneType: this.type =
     this.getClass.getConstructors.head.newInstance(pingen, c).asInstanceOf[this.type]
 
-  def fromPWMPort(port: PWMPortIO) {
+  def fromPort(port: PWMPortIO) {
     (pwm zip port.port)  foreach {case (pin, port) =>
       pin.outputPin(port)
     }

src/main/scala/devices/spi/SPIPins.scala

@@ -14,7 +14,7 @@ class SPIPins[T <: Pin] (pingen: ()=> T, c: SPIParamsBase) extends SPIBundle(c)
   override def cloneType: this.type =
     this.getClass.getConstructors.head.newInstance(pingen, c).asInstanceOf[this.type]
 
-  def fromSPIPort(spi: SPIPortIO, clock: Clock, reset: Bool,
+  def fromPort(spi: SPIPortIO, clock: Clock, reset: Bool,
     syncStages: Int = 0, driveStrength: Bool = Bool(false)) {
 
     withClockAndReset(clock, reset) {

src/main/scala/devices/uart/UARTPeriphery.scala

@@ -47,7 +47,7 @@ class UARTPins[T <: Pin] (pingen: () => T) extends Bundle {
   override def cloneType: this.type =
     this.getClass.getConstructors.head.newInstance(pingen).asInstanceOf[this.type]
 
-  def fromUARTPort(uart: UARTPortIO, clock: Clock, reset: Bool, syncStages: Int = 0) {
+  def fromPort(uart: UARTPortIO, clock: Clock, reset: Bool, syncStages: Int = 0) {
     withClockAndReset(clock, reset) {
       txd.outputPin(uart.txd)
       val rxd_t = rxd.inputPin()