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axi4: switch to new pipelined converters

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This commit is contained in:
Wesley W. Terpstra
2017-04-26 13:10:50 -07:00
parent 6eddf517a3
commit a24fa9b444
3 changed files with 38 additions and 15 deletions
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6
src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala
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@@ -197,8 +197,7 @@ class VC707AXIToPCIeX1(implicit p:Parameters) extends LazyModule
resources = Seq(Resource(device, "ranges")),
executable = true,
supportsWrite = TransferSizes(1, 256),
supportsRead = TransferSizes(1, 256),
interleavedId = Some(0))), // the Xilinx IP is friendly
supportsRead = TransferSizes(1, 256))),
beatBytes = 8)))
val control = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
@@ -206,8 +205,7 @@ class VC707AXIToPCIeX1(implicit p:Parameters) extends LazyModule
address = List(AddressSet(0x50000000L, 0x03ffffffL)),
resources = device.reg,
supportsWrite = TransferSizes(1, 4),
supportsRead = TransferSizes(1, 4),
interleavedId = Some(0))), // no read interleaving b/c AXI-lite
supportsRead = TransferSizes(1, 4))),
beatBytes = 4)))
val master = AXI4MasterNode(Seq(AXI4MasterPortParameters(