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axi4: switch to new pipelined converters

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This commit is contained in:
Wesley W. Terpstra
2017-04-26 13:10:50 -07:00
parent 6eddf517a3
commit a24fa9b444
3 changed files with 38 additions and 15 deletions
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28
src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala
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@ -26,9 +26,31 @@ class XilinxVC707PCIeX1(implicit p: Parameters) extends LazyModule {
val intnode = IntOutputNode()
val axi_to_pcie_x1 = LazyModule(new VC707AXIToPCIeX1)
axi_to_pcie_x1.slave := AXI4Buffer()(TLToAXI4(idBits=4)(slave))
axi_to_pcie_x1.control := AXI4Buffer()(AXI4Fragmenter(lite=true, maxInFlight=4)(TLToAXI4(idBits=0)(control)))
master := TLWidthWidget(8)(AXI4ToTL()(AXI4Fragmenter()(axi_to_pcie_x1.master)))
axi_to_pcie_x1.slave :=
AXI4Buffer()(
AXI4UserYanker()(
AXI4Deinterleaver(p(coreplex.CacheBlockBytes))(
AXI4IdIndexer(idBits=4)(
TLToAXI4(beatBytes=8)(
slave)))))
axi_to_pcie_x1.control :=
AXI4Buffer()(
AXI4UserYanker()(
AXI4Fragmenter()(
AXI4IdIndexer(idBits=0)(
TLToAXI4(beatBytes=4)(
control)))))
master :=
TLWidthWidget(8)(
AXI4ToTL()(
AXI4UserYanker(capMaxFlight=Some(8))(
AXI4Fragmenter()(
AXI4IdIndexer(idBits=0)(
axi_to_pcie_x1.master)))))
intnode := axi_to_pcie_x1.intnode
lazy val module = new LazyModuleImp(this) {