riscv/sifive-blocks
1
0
Fork 0
Code Releases Activity

GPIO: IOF should not override PUE and DS

Browse Source
This commit is contained in:
Megan Wachs 2017-11-08 15:15:32 -08:00
parent 90e6ea1d2d
commit 90404980b8
1 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/main/scala/devices/gpio/GPIO.scala
View File

@ -168,10 +168,10 @@ trait HasGPIOModuleContents extends MultiIOModule with HasRegMap {
val swPinCtrl = Wire(Vec(c.width, new EnhancedPinCtrl())) val swPinCtrl = Wire(Vec(c.width, new EnhancedPinCtrl()))
// This strips off the valid. // This strips off the valid.
val iof0Ctrl = Wire(Vec(c.width, new EnhancedPinCtrl())) val iof0Ctrl = Wire(Vec(c.width, new IOFCtrl()))
val iof1Ctrl = Wire(Vec(c.width, new EnhancedPinCtrl())) val iof1Ctrl = Wire(Vec(c.width, new IOFCtrl()))
val iofCtrl = Wire(Vec(c.width, new EnhancedPinCtrl())) val iofCtrl = Wire(Vec(c.width, new IOFCtrl()))
val iofPlusSwPinCtrl = Wire(Vec(c.width, new EnhancedPinCtrl())) val iofPlusSwPinCtrl = Wire(Vec(c.width, new EnhancedPinCtrl()))
for (pin <- 0 until c.width) { for (pin <- 0 until c.width) {