More Peripheral-to-pins cleanups
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@ -30,9 +30,9 @@ trait HasPeripheryUARTBundle {
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}
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def UARTtoGPIOPins(syncStages: Int = 0): Seq[UARTPinsIO] = uarts.map { u =>
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val pin = Module(new UARTGPIOPort(syncStages))
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pin.io.uart <> u
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pin.io.pins
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val pins = Module(new UARTGPIOPort(syncStages))
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pins.io.uart <> u
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pins.io.pins
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}
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}
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