diff --git a/src/main/scala/devices/terminal/Terminal.scala b/src/main/scala/devices/terminal/Terminal.scala
index fd496c2..dc3f34a 100644
--- a/src/main/scala/devices/terminal/Terminal.scala
+++ b/src/main/scala/devices/terminal/Terminal.scala
@@ -10,7 +10,7 @@ import freechips.rocketchip.regmapper._
 import freechips.rocketchip.subsystem.{BaseSubsystem}
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.util.AsyncQueue
-
+import sifive.blocks.util.NonBlockingEnqueue
 
 case class TerminalParams (
     address: BigInt
@@ -69,18 +69,8 @@ trait TerminalRegModule extends MultiIOModule with HasRegMap {
     term.io.write_data := crossing.io.deq.bits
     crossing.io.deq.ready := Bool(true) // terminal can read at every cycle
 
-    val writer_fn = (valid: Bool, data: UInt) => {
-        crossing.io.enq.valid := valid
-        crossing.io.enq.bits := data
-        Bool(true) // discards values if queue is full (see NonBlockingEnqueue)
-    }
-
     regmap(
-        0 -> Seq (
-            RegField.w(8, writer_fn, RegFieldDesc(
-                "write", "Write an ASCII character to the terminal."
-            ))
-        )
+        0 -> NonBlockingEnqueue(crossing.io.enq)
     )
 }