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GPIO/SPI/I2C: Add sync stages in place of dummy variable since we need them and they are more useful.

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This commit is contained in:
Megan Wachs
2017-06-12 17:53:08 -07:00
parent d4bb8a77ea
commit 7c118790cb
2 changed files with 4 additions and 4 deletions
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4
src/main/scala/devices/spi/SPIPeriphery.scala
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@@ -23,8 +23,8 @@ trait HasPeripherySPI extends HasSystemNetworks {
trait HasPeripherySPIBundle {
val spis: HeterogeneousBag[SPIPortIO]
def SPItoGPIOPins(dummy: Int = 1): Seq[SPIGPIOPort] = spis.map { s =>
val pin = Module(new SPIGPIOPort(s.c))
def SPItoGPIOPins(sync_stages: Int = 0): Seq[SPIGPIOPort] = spis.map { s =>
val pin = Module(new SPIGPIOPort(s.c, sync_stages))
pin.io.spi <> s
pin
}

4
src/main/scala/devices/uart/UARTPeriphery.scala
View File

@@ -29,8 +29,8 @@ trait HasPeripheryUARTBundle {
uarts.foreach { _.rxd := UInt(1) }
}
def UARTtoGPIOPins(dummy: Int = 1): Seq[UARTGPIOPort] = uarts.map { u =>
val pin = Module(new UARTGPIOPort)
def UARTtoGPIOPins(sync_stages: Int = 0): Seq[UARTGPIOPort] = uarts.map { u =>
val pin = Module(new UARTGPIOPort(sync_stages))
pin.io.uart <> u
pin
}