riscv/sifive-blocks
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peripheral_options: Actually compiles

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This commit is contained in:
Megan Wachs 2017-06-09 13:53:22 -07:00
parent 29226701a8
commit 79f64de12c
2 changed files with 5 additions and 4 deletions
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5
src/main/scala/devices/gpio/GPIOPeriphery.scala
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@ -10,6 +10,7 @@ import rocketchip.{
HasTopLevelNetworksModule
}
import uncore.tilelink2.TLFragmenter
import util.HeterogeneousBag
case object PeripheryGPIOKey extends Field[Seq[GPIOParams]]
@ -25,13 +26,13 @@ trait HasPeripheryGPIO extends HasTopLevelNetworks {
trait HasPeripheryGPIOBundle extends HasTopLevelNetworksBundle {
val outer: HasPeripheryGPIO
val gpio = HeterogeneousBag(outer.gpioParams(map(new GPIOPortIO(_))))
val gpio = HeterogeneousBag(outer.gpioParams.map(new GPIOPortIO(_)))
}
trait HasPeripheryGPIOModule extends HasTopLevelNetworksModule {
val outer: HasPeripheryGPIO
val io: HasPeripheryGPIOBundle
(io.gpio zip outer.gpio) foreach { case (io, device) =>
io.gpio <> device.module.io.port
io <> device.module.io.port
}
}

4
src/main/scala/devices/spi/SPIPeriphery.scala
View File

@ -52,7 +52,7 @@ trait HasPeripherySPIFlash extends HasTopLevelNetworks {
trait HasPeripherySPIFlashBundle extends HasTopLevelNetworksBundle {
val outer: HasPeripherySPIFlash
val qspi = HeterogenousBag(outer.spiFlashParams.map(new SPIPortIO(_)))
val qspi = HeterogeneousBag(outer.spiFlashParams.map(new SPIPortIO(_)))
}
trait HasPeripherySPIFlashModule extends HasTopLevelNetworksModule {
@ -60,7 +60,7 @@ trait HasPeripherySPIFlashModule extends HasTopLevelNetworksModule {
val io: HasPeripherySPIFlashBundle
(io.qspi zip outer.qspi) foreach { case (io, device) =>
io.qspi <> device.module.io.port
io <> device.module.io.port
}
}