riscv/sifive-blocks
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spi: Make memory mapped interface depth a parameter

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This commit is contained in:
Megan Wachs 2017-08-20 12:39:38 -07:00
parent a814cba04f
commit 70c25846b8
2 changed files with 3 additions and 1 deletions
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2
src/main/scala/devices/spi/SPIPeriphery.scala
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@ -43,7 +43,7 @@ trait HasPeripherySPIFlash extends HasPeripheryBus with HasInterruptBus {
qspi.rnode := pbus.toVariableWidthSlaves qspi.rnode := pbus.toVariableWidthSlaves
qspi.fnode := qspi.fnode :=
TLFragmenter(1, pbus.blockBytes)( TLFragmenter(1, pbus.blockBytes)(
TLBuffer(BufferParams(8), BufferParams.none)( TLBuffer(BufferParams(params.fBufferDepth), BufferParams.none)(
pbus.toFixedWidthSlaves)) pbus.toFixedWidthSlaves))
ibus.fromSync := qspi.intnode ibus.fromSync := qspi.intnode
qspi qspi

2
src/main/scala/devices/spi/TLSPIFlash.scala
View File

@ -11,6 +11,7 @@ import freechips.rocketchip.util.HeterogeneousBag
trait SPIFlashParamsBase extends SPIParamsBase { trait SPIFlashParamsBase extends SPIParamsBase {
val fAddress: BigInt val fAddress: BigInt
val fSize: BigInt val fSize: BigInt
val fBufferDepth: Int
val insnAddrBytes: Int val insnAddrBytes: Int
val insnPadLenBits: Int val insnPadLenBits: Int
@ -22,6 +23,7 @@ trait SPIFlashParamsBase extends SPIParamsBase {
case class SPIFlashParams( case class SPIFlashParams(
rAddress: BigInt, rAddress: BigInt,
fAddress: BigInt, fAddress: BigInt,
fBufferDepth: Int = 0,
rSize: BigInt = 0x1000, rSize: BigInt = 0x1000,
fSize: BigInt = 0x20000000, fSize: BigInt = 0x20000000,
rxDepth: Int = 8, rxDepth: Int = 8,