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i2c: Allow irq to be cleared

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This commit is contained in:
Megan Wachs 2018-02-16 15:49:09 -08:00
parent 14ffd35f5c
commit 6c5b80671c
1 changed files with 2 additions and 2 deletions
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src/main/scala/devices/i2c/I2C.scala
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@ -488,16 +488,16 @@ trait HasI2CModuleContents extends MultiIOModule with HasRegMap {
// hack: b/c the same register offset is used to write cmd and read status // hack: b/c the same register offset is used to write cmd and read status
val nextCmd = Wire(UInt(8.W)) val nextCmd = Wire(UInt(8.W))
nextCmd := cmd.asUInt
cmd := (new CommandBundle).fromBits(nextCmd) cmd := (new CommandBundle).fromBits(nextCmd)
nextCmd := cmd.asUInt & 0xFE.U // clear IRQ_ACK bit (essentially 1 cycle pulse b/c it is overwritten by regmap below)
// Note: This wins over the regmap update of nextCmd (even if something tries to write them to 1, these values take priority).
when (cmdAck || arbLost) { when (cmdAck || arbLost) {
cmd.start := false.B // clear command bits when done cmd.start := false.B // clear command bits when done
cmd.stop := false.B // or when aribitration lost cmd.stop := false.B // or when aribitration lost
cmd.read := false.B cmd.read := false.B
cmd.write := false.B cmd.write := false.B
} }
cmd.irqAck := false.B // clear IRQ_ACK bit (essentially 1 cycle pulse b/c it is overwritten by regmap below)
status.receivedAck := receivedAck status.receivedAck := receivedAck
when (stopCond) { when (stopCond) {