riscv/sifive-blocks
1
0
Fork 0
Code Releases Activity

xilinx ip: adjust to new diplomacy API

Browse Source
This commit is contained in:
Wesley W. Terpstra
2017-01-30 11:33:30 -08:00
parent d61d86e084
commit 5b6760394d
2 changed files with 10 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala
View File

@@ -167,27 +167,27 @@ class vc707axi_to_pcie_x1() extends BlackBox
class VC707AXIToPCIeX1(implicit p:Parameters) extends LazyModule
{
val slave = AXI4SlaveNode(AXI4SlavePortParameters(
val slave = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
slaves = Seq(AXI4SlaveParameters(
address = List(AddressSet(0x60000000L, 0x1fffffffL)),
executable = true,
supportsWrite = TransferSizes(1, 256),
supportsRead = TransferSizes(1, 256),
interleavedId = Some(0))), // the Xilinx IP is friendly
beatBytes = 8))
beatBytes = 8)))
val control = AXI4SlaveNode(AXI4SlavePortParameters(
val control = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
slaves = Seq(AXI4SlaveParameters(
address = List(AddressSet(0x50000000L, 0x03ffffffL)),
supportsWrite = TransferSizes(1, 4),
supportsRead = TransferSizes(1, 4),
interleavedId = Some(0))), // no read interleaving b/c AXI-lite
beatBytes = 4))
beatBytes = 4)))
val master = AXI4MasterNode(AXI4MasterPortParameters(
val master = AXI4MasterNode(Seq(AXI4MasterPortParameters(
masters = Seq(AXI4MasterParameters(
id = IdRange(0, 1),
aligned = false))))
aligned = false)))))
lazy val module = new LazyModuleImp(this) {
// The master on the control port must be AXI-lite