riscv/sifive-blocks
1
0
Fork 0
Code Releases Activity

diplomacy: update to new API (#40)

Browse Source
This commit is contained in:
Wesley W. Terpstra
2017-09-27 16:33:18 -07:00
committed by GitHub
parent fe65a87c5c
commit 4fcf349adb
16 changed files with 50 additions and 58 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src/main/scala/devices/spi/SPIPeriphery.scala
View File

@ -4,7 +4,7 @@ package sifive.blocks.devices.spi
import Chisel._
import freechips.rocketchip.config.Field
import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp,BufferParams}
import freechips.rocketchip.diplomacy.{LazyModule,LazyModuleImp,BufferParams}
import freechips.rocketchip.tilelink.{TLFragmenter,TLBuffer}
import freechips.rocketchip.util.HeterogeneousBag
@ -25,7 +25,7 @@ trait HasPeripherySPIBundle {
}
trait HasPeripherySPIModuleImp extends LazyMultiIOModuleImp with HasPeripherySPIBundle {
trait HasPeripherySPIModuleImp extends LazyModuleImp with HasPeripherySPIBundle {
val outer: HasPeripherySPI
val spi = IO(HeterogeneousBag(outer.spiParams.map(new SPIPortIO(_))))
@ -55,7 +55,7 @@ trait HasPeripherySPIFlashBundle {
}
trait HasPeripherySPIFlashModuleImp extends LazyMultiIOModuleImp with HasPeripherySPIFlashBundle {
trait HasPeripherySPIFlashModuleImp extends LazyModuleImp with HasPeripherySPIFlashBundle {
val outer: HasPeripherySPIFlash
val qspi = IO(HeterogeneousBag(outer.spiFlashParams.map(new SPIPortIO(_))))

14
src/main/scala/devices/spi/TLSPI.scala
View File

@ -47,15 +47,12 @@ case class SPIParams(
require(sampleDelay >= 0)
}
class SPITopBundle(val i: HeterogeneousBag[Vec[Bool]], val r: HeterogeneousBag[TLBundle]) extends Bundle
class SPITopModule[B <: SPITopBundle](c: SPIParamsBase, bundle: => B, outer: TLSPIBase)
class SPITopModule(c: SPIParamsBase, outer: TLSPIBase)
extends LazyModuleImp(outer) {
val io = new Bundle {
val io = IO(new Bundle {
val port = new SPIPortIO(c)
val tl = bundle
}
})
val ctrl = Reg(init = SPIControl.init(c))
@ -72,7 +69,8 @@ class SPITopModule[B <: SPITopBundle](c: SPIParamsBase, bundle: => B, outer: TLS
val ie = Reg(init = new SPIInterrupts().fromBits(Bits(0)))
val ip = fifo.io.ip
io.tl.i(0)(0) := (ip.txwm && ie.txwm) || (ip.rxwm && ie.rxwm)
val (io_int, _) = outer.intnode.out(0)
io_int(0) := (ip.txwm && ie.txwm) || (ip.rxwm && ie.rxwm)
protected val regmapBase = Seq(
SPICRs.sckdiv -> Seq(RegField(c.divisorBits, ctrl.sck.div)),
@ -115,7 +113,7 @@ abstract class TLSPIBase(w: Int, c: SPIParamsBase)(implicit p: Parameters) exten
}
class TLSPI(w: Int, c: SPIParams)(implicit p: Parameters) extends TLSPIBase(w,c)(p) {
lazy val module = new SPITopModule(c, new SPITopBundle(intnode.bundleOut, rnode.bundleIn), this) {
lazy val module = new SPITopModule(c, this) {
mac.io.link <> fifo.io.link
rnode.regmap(regmapBase:_*)
}

30
src/main/scala/devices/spi/TLSPIFlash.scala
View File

@ -41,16 +41,13 @@ case class SPIFlashParams(
require(sampleDelay >= 0)
}
class SPIFlashTopBundle(i: HeterogeneousBag[Vec[Bool]], r: HeterogeneousBag[TLBundle], val f: HeterogeneousBag[TLBundle]) extends SPITopBundle(i, r)
class SPIFlashTopModule[B <: SPIFlashTopBundle]
(c: SPIFlashParamsBase, bundle: => B, outer: TLSPIFlashBase)
extends SPITopModule(c, bundle, outer) {
class SPIFlashTopModule(c: SPIFlashParamsBase, outer: TLSPIFlashBase)
extends SPITopModule(c, outer) {
val flash = Module(new SPIFlashMap(c))
val arb = Module(new SPIArbiter(c, 2))
private val f = io.tl.f.head
private val (f, _) = outer.fnode.in(0)
// Tie unused channels
f.b.valid := Bool(false)
f.c.ready := Bool(true)
@ -68,7 +65,7 @@ class SPIFlashTopModule[B <: SPIFlashTopBundle]
flash.io.addr.valid := f.a.valid
f.a.ready := flash.io.addr.ready
f.d.bits := outer.fnode.edgesIn.head.AccessAck(a, flash.io.data.bits)
f.d.bits := outer.fnode.edges.in.head.AccessAck(a, flash.io.data.bits)
f.d.valid := flash.io.data.valid
flash.io.data.ready := f.d.ready
@ -96,18 +93,19 @@ class SPIFlashTopModule[B <: SPIFlashTopBundle]
abstract class TLSPIFlashBase(w: Int, c: SPIFlashParamsBase)(implicit p: Parameters) extends TLSPIBase(w,c)(p) {
require(isPow2(c.fSize))
val fnode = TLManagerNode(1, TLManagerParameters(
address = Seq(AddressSet(c.fAddress, c.fSize-1)),
resources = device.reg("mem"),
regionType = RegionType.UNCACHED,
executable = true,
supportsGet = TransferSizes(1, 1),
fifoId = Some(0)))
val fnode = TLManagerNode(Seq(TLManagerPortParameters(
managers = Seq(TLManagerParameters(
address = Seq(AddressSet(c.fAddress, c.fSize-1)),
resources = device.reg("mem"),
regionType = RegionType.UNCACHED,
executable = true,
supportsGet = TransferSizes(1, 1),
fifoId = Some(0))),
beatBytes = 1)))
}
class TLSPIFlash(w: Int, c: SPIFlashParams)(implicit p: Parameters) extends TLSPIFlashBase(w,c)(p) {
lazy val module = new SPIFlashTopModule(c,
new SPIFlashTopBundle(intnode.bundleOut, rnode.bundleIn, fnode.bundleIn), this) {
lazy val module = new SPIFlashTopModule(c, this) {
arb.io.inner(0) <> flash.io.link
arb.io.inner(1) <> fifo.io.link