riscv/sifive-blocks
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diplomacy: update to new API (#40)

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This commit is contained in:
Wesley W. Terpstra
2017-09-27 16:33:18 -07:00
committed by GitHub
parent fe65a87c5c
commit 4fcf349adb
16 changed files with 50 additions and 58 deletions
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3
src/main/scala/devices/mockaon/MockAON.scala
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@ -2,6 +2,7 @@
package sifive.blocks.devices.mockaon
import Chisel._
import chisel3.experimental.MultiIOModule
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.regmapper._
import freechips.rocketchip.tilelink._
@ -49,7 +50,7 @@ trait HasMockAONBundleContents extends Bundle {
val resetCauses = new ResetCauses().asInput
}
trait HasMockAONModuleContents extends Module with HasRegMap {
trait HasMockAONModuleContents extends MultiIOModule with HasRegMap {
val io: HasMockAONBundleContents
val params: MockAONParams
val c = params

4
src/main/scala/devices/mockaon/MockAONPeriphery.scala
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@ -7,7 +7,7 @@ import freechips.rocketchip.util.SynchronizerShiftReg
import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
import freechips.rocketchip.devices.debug.HasPeripheryDebug
import freechips.rocketchip.devices.tilelink.HasPeripheryClint
import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
import freechips.rocketchip.tilelink.{IntXing, TLAsyncCrossingSource}
import freechips.rocketchip.util.ResetCatchAndSync
@ -32,7 +32,7 @@ trait HasPeripheryMockAONBundle {
}
}
trait HasPeripheryMockAONModuleImp extends LazyMultiIOModuleImp with HasPeripheryMockAONBundle {
trait HasPeripheryMockAONModuleImp extends LazyModuleImp with HasPeripheryMockAONBundle {
val outer: HasPeripheryMockAON
val aon = IO(new MockAONWrapperBundle)

19
src/main/scala/devices/mockaon/MockAONWrapper.scala
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@ -30,8 +30,6 @@ class MockAONWrapperBundle extends Bundle {
class MockAONWrapper(w: Int, c: MockAONParams)(implicit p: Parameters) extends LazyModule {
val node = TLAsyncInputNode()
val intnode = IntOutputNode()
val aon = LazyModule(new TLMockAON(w, c))
// We only need to isolate the signals
@ -45,20 +43,18 @@ class MockAONWrapper(w: Int, c: MockAONParams)(implicit p: Parameters) extends L
val isolation = LazyModule(new TLIsolation(fOut = isoOut, fIn = isoIn))
val crossing = LazyModule(new TLAsyncCrossingSink(depth = 1))
isolation.node := node
val node: TLAsyncInwardNode = isolation.node
crossing.node := isolation.node
val crossing_monitor = (aon.node := crossing.node)
aon.node := crossing.node
// crossing lives outside in Periphery
intnode := aon.intnode
val intnode: IntOutwardNode = aon.intnode
lazy val module = new LazyModuleImp(this) {
val io = new MockAONWrapperBundle {
val in = node.bundleIn
val ip = intnode.bundleOut
val io = IO(new MockAONWrapperBundle {
val rtc = Clock(OUTPUT)
val ndreset = Bool(INPUT)
}
})
val aon_io = aon.module.io
val pins = io.pins
@ -122,11 +118,6 @@ class MockAONWrapper(w: Int, c: MockAONParams)(implicit p: Parameters) extends L
crossing.module.clock := lfclk
crossing.module.reset := crossing_slave_reset
crossing_monitor.foreach { lm =>
lm.module.clock := lfclk
lm.module.reset := crossing_slave_reset
}
// Note that aon.moff.corerst is synchronous
// to aon.module.clock, so this is safe.
isolation.module.io.iso_out := aon.module.io.moff.corerst