riscv/sifive-blocks
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diplomacy: update to new API (#40)

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This commit is contained in:
Wesley W. Terpstra
2017-09-27 16:33:18 -07:00
committed by GitHub
parent fe65a87c5c
commit 4fcf349adb
16 changed files with 50 additions and 58 deletions
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3
src/main/scala/devices/gpio/GPIO.scala
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@ -2,6 +2,7 @@
package sifive.blocks.devices.gpio
import Chisel._
import chisel3.experimental.MultiIOModule
import sifive.blocks.devices.pinctrl.{PinCtrl, Pin, BasePin, EnhancedPin, EnhancedPinCtrl}
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.util.SynchronizerShiftReg
@ -87,7 +88,7 @@ trait HasGPIOBundleContents extends Bundle {
val port = new GPIOPortIO(params)
}
trait HasGPIOModuleContents extends Module with HasRegMap {
trait HasGPIOModuleContents extends MultiIOModule with HasRegMap {
val io: HasGPIOBundleContents
val params: GPIOParams
val c = params