From 48d8524c4aa615521c3d35c388fe2025b1b05639 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Klemens=20Sch=C3=B6lhorn?= Date: Mon, 30 Apr 2018 22:50:39 +0200 Subject: [PATCH] Move terminal into own clock domain using AsyncQueue --- .../scala/devices/terminal/Terminal.scala | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/src/main/scala/devices/terminal/Terminal.scala b/src/main/scala/devices/terminal/Terminal.scala index e557fae..fd496c2 100644 --- a/src/main/scala/devices/terminal/Terminal.scala +++ b/src/main/scala/devices/terminal/Terminal.scala @@ -9,6 +9,7 @@ import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} import freechips.rocketchip.regmapper._ import freechips.rocketchip.subsystem.{BaseSubsystem} import freechips.rocketchip.tilelink._ +import freechips.rocketchip.util.AsyncQueue case class TerminalParams ( @@ -56,10 +57,22 @@ trait TerminalRegModule extends MultiIOModule with HasRegMap { io.port_sys <> term.io.sys io.port_dvi <> term.io.dvi + val crossing = Module(new AsyncQueue(UInt(8.W), depth=1, safe=false)) + + crossing.io.enq_clock := clock + crossing.io.enq_reset := Bool(false) + crossing.io.deq_clock := io.port_sys.clk + crossing.io.deq_reset := Bool(false) + + // wire up dequeue to terminal io + term.io.write_enable := crossing.io.deq.valid + term.io.write_data := crossing.io.deq.bits + crossing.io.deq.ready := Bool(true) // terminal can read at every cycle + val writer_fn = (valid: Bool, data: UInt) => { - term.io.write_enable := valid - term.io.write_data := data - Bool(true) // terminal can read at every cycle + crossing.io.enq.valid := valid + crossing.io.enq.bits := data + Bool(true) // discards values if queue is full (see NonBlockingEnqueue) } regmap(